Display device

ABSTRACT

A display device comprises a first line extending in a first direction, a second line spaced apart from the first line in a second direction, sub-pixels including emission areas between the first line and the second line, light-emitting elements in light-emitting element arrangement areas in the emission areas, a bank pattern overlapping with the first line and the second line, and defining openings corresponding to the light-emitting element arrangement areas, and a bank surrounding the emission areas, and overlapping with the first line, the second line, and the bank pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean patentapplication No. 10-2022-0032979 filed on Mar. 16, 2022 in the KoreanIntellectual Property Office, the entire disclosure of which isincorporated herein by reference.

BACKGROUND 1. Field

The present disclosure generally relates to a display device.

2. Related Art

Recently, interest in information displays has been increased.Accordingly, research and development of display devices have beencontinuously conducted.

SUMMARY

Embodiments provide a display device capable of reducing or preventingoverflow of a light-emitting element ink including light-emittingelements.

In accordance with an aspect of the present disclosure, there isprovided a display device including a first line extending in a firstdirection, a second line spaced apart from the first line in a seconddirection, sub-pixels including emission areas between the first lineand the second line, light-emitting elements in light-emitting elementarrangement areas in the emission areas, a bank pattern overlapping withthe first line and the second line, and defining openings correspondingto the light-emitting element arrangement areas, and a bank surroundingthe emission areas, and overlapping with the first line, the secondline, and the bank pattern.

The second line may extend in the first direction, wherein the bankpattern includes a first pattern part overlapping the first line, andcontinuously formed along the first direction at a periphery of theemission areas, a second pattern part overlapping the second line, andcontinuously formed along the first direction at the periphery of theemission areas, and third pattern parts at respective sides of thelight-emitting element arrangement areas in the first direction, andextending in the second direction.

The bank may be continuously formed along the first direction at aportion overlapping with the first pattern part and the second patternpart.

The first line may be a scan line configured to transmit a scan signal,wherein the second line is a power line configured to transmit a firstpower voltage or a second power voltage.

The sub-pixels may include a first alignment electrode at a periphery offirst end portions of the light-emitting elements, and extending in thesecond direction, wherein the first alignment electrode includes an endportion at a portion of a non-emission area adjacent to an emission areaof a corresponding sub-pixel in the second direction.

The first alignment electrode may be electrically connected to the firstend portions of the light-emitting elements.

The sub-pixels may further include a pixel circuit electricallyconnected to the first alignment electrode.

The sub-pixels may further include a second alignment electrode at aperiphery of second end portions of the light-emitting elements, andextending in the second direction.

The display device may further include a power line electricallyconnected to the second alignment electrode.

The sub-pixels may include a first sub-pixel, a second sub-pixel, and athird sub-pixel, which constitute one pixel, and respectively mayinclude a first emission area, a second emission area, and a thirdemission area, and that are arranged in the first direction between thefirst line and the second line.

The first line, the bank pattern, and the bank completely may overlapwith each other in a non-emission area immediately adjacent to firstedge areas of the first emission area, the second emission area, and thethird emission area, wherein the second line, the bank pattern, and thebank completely overlap with each other in a non-emission areaimmediately adjacent to second edge areas of the first emission area,the second emission area, and the third emission area.

The first sub-pixel may further include a first pixel circuitelectrically connected to light-emitting elements in the first emissionarea among the light-emitting elements, wherein the second sub-pixelfurther includes a second pixel circuit electrically connected tolight-emitting elements in the second emission area among thelight-emitting elements, and wherein the third sub-pixel furtherincludes a third pixel circuit electrically connected to light-emittingelements in the third emission area among the light-emitting elements.

The first pixel circuit, the second pixel circuit, and the third pixelcircuit may be arranged in the second direction.

The second line may be between the second pixel circuit and the thirdpixel circuit.

The first pixel circuit and the third pixel circuit may be between thefirst line and the second line.

The sub-pixels may include a light-emitting unit including at least onelight-emitting element in a corresponding emission area among thelight-emitting elements, and electrodes electrically connected to the atleast one light-emitting element, and a pixel circuit including circuitelements electrically connected to the light-emitting unit.

The display device may further include a circuit layer including pixelcircuits of the sub-pixels, the first line, and the second line, and adisplay layer overlapping with the circuit layer, and includinglight-emitting units of the sub-pixels.

The circuit layer may include conductive layers sequentially arrangedalong a third direction crossing the first direction and the seconddirection, wherein a conductive layer closest to the display layer amongthe conductive layers includes the first line and the second line.

The display device may further include at least two pixels eachincluding sub-pixels among the sub-pixels, the at least two pixels beingarranged in the first direction, wherein the bank pattern includesindividual patterns formed by separating patterns corresponding to eachof the at least two pixels from each other, or includes an integratedpattern in which patterns corresponding to each of the at least twopixels are integrally formed.

In accordance with another aspect of the present disclosure, there isprovided a display device including a first line and a second lineextending in a first direction, and spaced apart from each other in asecond direction, a first sub-pixel including first light-emittingelements in a first emission area between the first line and the secondline, a second sub-pixel including second light-emitting elements in asecond emission area that is adjacent to the first emission area in thefirst direction, and that is between the first line and the second line,a third sub-pixel including third light-emitting elements in a thirdemission area that is adjacent to the second emission area in the firstdirection, and that is between the first line and the second line, abank pattern overlapping with the first line and the second line, anddefining openings respectively corresponding to light-emitting elementarrangement areas in the first emission area, the second emission area,and the third emission area, and a bank surrounding the first to thirdemission areas, and overlapping with the first line, the second line,and the bank pattern, wherein, at a portion immediately adjacent to bothends of the first emission area, the second emission area, and the thirdemission area in the second direction, the bank pattern and the bankoverlap with the first line and the second line and are continuouslyformed along the first direction.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described more fully hereinafter with referenceto the accompanying drawings; however, they may be embodied in differentforms and should not be construed as limited to the embodiments setforth herein. Rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the embodiments to those skilled in the art.

In the drawing figures, dimensions may be exaggerated for clarity ofillustration. It will be understood that when an element is referred toas being “between” two elements, it can be the only element between thetwo elements, or one or more intervening elements may also be present.Like reference numerals refer to like elements throughout.

FIG. 1 is a perspective view illustrating a light-emitting element inaccordance with one or more embodiments of the present disclosure.

FIG. 2 is a sectional view illustrating the light-emitting element inaccordance with one or more embodiments of the present disclosure.

FIG. 3 is a plan view illustrating a display device in accordance withone or more embodiments of the present disclosure.

FIGS. 4 and 5 are circuit diagrams illustrating sub-pixels in accordancewith embodiments of the present disclosure.

FIG. 6 is a plan view illustrating a display area in accordance with oneor more embodiments of the present disclosure.

FIG. 7 is a sectional view illustrating a display area in accordancewith one or more embodiments of the present disclosure.

FIG. 8 is a plan view illustrating a circuit layer of the display areain accordance with one or more embodiments of the present disclosure.

FIG. 9 is a plan view illustrating a display layer of the display areain accordance with one or more embodiments of the present disclosure.

FIGS. 10 and 11 are plan views illustrating display layers of thedisplay area in accordance with embodiments of the present disclosure.

FIG. 12 is a sectional view illustrating a display area in accordancewith one or more embodiments of the present disclosure.

DETAILED DESCRIPTION

Aspects of some embodiments of the present disclosure and methods ofaccomplishing the same may be understood more readily by reference tothe detailed description of embodiments and the accompanying drawings.Hereinafter, embodiments will be described in more detail with referenceto the accompanying drawings. The described embodiments, however, mayhave various modifications and may be embodied in various differentforms, and should not be construed as being limited to only theillustrated embodiments herein. Rather, these embodiments are providedas examples so that this disclosure will be thorough and complete, andwill fully convey the aspects of the present disclosure to those skilledin the art, and it should be understood that the present disclosurecovers all the modifications, equivalents, and replacements within theidea and technical scope of the present disclosure. Accordingly,processes, elements, and techniques that are not necessary to thosehaving ordinary skill in the art for a complete understanding of theaspects of the present disclosure may not be described.

Unless otherwise noted, like reference numerals, characters, orcombinations thereof denote like elements throughout the attacheddrawings and the written description, and thus, descriptions thereofwill not be repeated. Further, parts that are not related to, or thatare irrelevant to, the description of the embodiments might not be shownto make the description clear.

In the drawings, the relative sizes of elements, layers, and regions maybe exaggerated for clarity. Additionally, the use of cross-hatchingand/or shading in the accompanying drawings is generally provided toclarify boundaries between adjacent elements. As such, neither thepresence nor the absence of cross-hatching or shading conveys orindicates any preference or requirement for particular materials,material properties, dimensions, proportions, commonalities betweenillustrated elements, and/or any other characteristic, attribute,property, etc., of the elements, unless specified.

Various embodiments are described herein with reference to sectionalillustrations that are schematic illustrations of embodiments and/orintermediate structures. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Further, specific structural orfunctional descriptions disclosed herein are merely illustrative for thepurpose of describing embodiments according to the concept of thepresent disclosure. Thus, embodiments disclosed herein should not beconstrued as limited to the particular illustrated shapes of regions,but are to include deviations in shapes that result from, for instance,manufacturing.

For example, an implanted region illustrated as a rectangle will,typically, have rounded or curved features and/or a gradient of implantconcentration at its edges rather than a binary change from implanted tonon-implanted region. Likewise, a buried region formed by implantationmay result in some implantation in the region between the buried regionand the surface through which the implantation takes place.

Thus, the regions illustrated in the drawings are schematic in natureand their shapes are not intended to illustrate the actual shape of aregion of a device and are not intended to be limiting. Additionally, asthose skilled in the art would realize, the described embodiments may bemodified in various different ways, all without departing from thespirit or scope of the present disclosure.

Spatially relative terms, such as “beneath,” “below,” “lower,” “under,”“above,” “upper,” and the like, may be used herein for ease ofexplanation to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or in operation, in additionto the orientation depicted in the figures. For example, if the devicein the figures is turned over, elements described as “below” or“beneath” or “under” other elements or features would then be oriented“above” the other elements or features. Thus, the example terms “below”and “under” can encompass both an orientation of above and below. Thedevice may be otherwise oriented (e.g., rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein shouldbe interpreted accordingly. Similarly, when a first part is described asbeing arranged “on” a second part, this indicates that the first part isarranged at an upper side or a lower side of the second part without thelimitation to the upper side thereof on the basis of the gravitydirection.

Further, in this specification, the phrase “on a plane,” or “plan view,”means viewing a target portion from the top, and the phrase “on across-section” means viewing a cross-section formed by verticallycutting a target portion from the side.

It will be understood that when an element, layer, region, or componentis referred to as being “formed on,” “on,” “connected to,” or “coupledto” another element, layer, region, or component, it can be directlyformed on, on, connected to, or coupled to the other element, layer,region, or component, or indirectly formed on, on, connected to, orcoupled to the other element, layer, region, or component such that oneor more intervening elements, layers, regions, or components may bepresent. In addition, this may collectively mean a direct or indirectcoupling or connection and an integral or non-integral coupling orconnection. For example, when a layer, region, or component is referredto as being “electrically connected” or “electrically coupled” toanother layer, region, or component, it can be directly electricallyconnected or coupled to the other layer, region, and/or component orintervening layers, regions, or components may be present. The term“connection” may inclusively mean physical and/or electrical connection,may inclusively mean direct connection and indirect connection, and mayinclusively mean integrated connection and non-integrated connection.However, “directly connected/directly coupled,” or “directly on,” refersto one component directly connecting or coupling another component, orbeing on another component, without an intermediate component. Inaddition, in the present specification, when a portion of a layer, afilm, an area, a plate, or the like is formed on another portion, aforming direction is not limited to an upper direction but includesforming the portion on a side surface or in a lower direction. On thecontrary, when a portion of a layer, a film, an area, a plate, or thelike is formed “under” another portion, this includes not only a casewhere the portion is “directly beneath” another portion but also a casewhere there is further another portion between the portion and anotherportion. Meanwhile, other expressions describing relationships betweencomponents such as “between,” “immediately between” or “adjacent to” and“directly adjacent to” may be construed similarly. In addition, it willalso be understood that when an element or layer is referred to as being“between” two elements or layers, it can be the only element or layerbetween the two elements or layers, or one or more intervening elementsor layers may also be present.

For the purposes of this disclosure, expressions such as “at least oneof,” when preceding a list of elements, modify the entire list ofelements and do not modify the individual elements of the list. Forexample, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,”and “at least one selected from the group consisting of X, Y, and Z” maybe construed as X only, Y only, Z only, any combination of two or moreof X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ, or anyvariation thereof. Similarly, the expression such as “at least one of Aand B” may include A, B, or A and B. As used herein, “or” generallymeans “and/or,” and the term “and/or” includes any and all combinationsof one or more of the associated listed items. For example, theexpression such as “A and/or B” may include A, B, or A and B.

It will be understood that, although the terms “first,” “second,”“third,” etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, a first element, component, region, layer or sectiondescribed below could be termed a second element, component, region,layer or section, without departing from the spirit and scope of thepresent disclosure. The description of an element as a “first” elementmay not require or imply the presence of a second element or otherelements. The terms “first”, “second”, etc. may also be used herein todifferentiate different categories or sets of elements. For conciseness,the terms “first”, “second”, etc. may represent “first-category (orfirst-set)”, “second-category (or second-set)”, etc., respectively.

In the examples, the x-axis, the y-axis, and/or the z-axis are notlimited to three axes of a rectangular coordinate system, and may beinterpreted in a broader sense. For example, the x-axis, the y-axis, andthe z-axis may be perpendicular to one another, or may representdifferent directions that are not perpendicular to one another. The sameapplies for first, second, and/or third directions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentdisclosure. As used herein, the singular forms “a” and “an” are intendedto include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “have,” “having,” “includes,” and“including,” when used in this specification, specify the presence ofthe stated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

As used herein, the term “substantially,” “about,” “approximately,” andsimilar terms are used as terms of approximation and not as terms ofdegree, and are intended to account for the inherent deviations inmeasured or calculated values that would be recognized by those ofordinary skill in the art. “About” or “approximately,” as used herein,is inclusive of the stated value and means within an acceptable range ofdeviation for the particular value as determined by one of ordinaryskill in the art, considering the measurement in question and the errorassociated with measurement of the particular quantity (i.e., thelimitations of the measurement system). For example, “about” may meanwithin one or more standard deviations, or within ±30%, 20%, 10%, 5% ofthe stated value. Further, the use of “may” when describing embodimentsof the present disclosure refers to “one or more embodiments of thepresent disclosure.”

Also, any numerical range disclosed and/or recited herein is intended toinclude all sub-ranges of the same numerical precision subsumed withinthe recited range. For example, a range of “1.0 to 10.0” is intended toinclude all subranges between (and including) the recited minimum valueof 1.0 and the recited maximum value of 10.0, that is, having a minimumvalue equal to or greater than 1.0 and a maximum value equal to or lessthan 10.0, such as, for example, 2.4 to 7.6. Any maximum numericallimitation recited herein is intended to include all lower numericallimitations subsumed therein, and any minimum numerical limitationrecited in this specification is intended to include all highernumerical limitations subsumed therein. Accordingly, Applicant reservesthe right to amend this specification, including the claims, toexpressly recite any sub-range subsumed within the ranges expresslyrecited herein. All such ranges are intended to be inherently describedin this specification such that amending to expressly recite any suchsubranges would comply with the requirements of 35 U.S.C. § 112(a) and35 U.S.C. § 132(a).

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present disclosure belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present specification, and should not be interpreted in an idealizedor overly formal sense, unless expressly so defined herein.

FIG. 1 is a perspective view illustrating a light-emitting element LD inaccordance with one or more embodiments of the present disclosure. FIG.2 is a sectional view illustrating the light-emitting element LD inaccordance with one or more embodiments of the present disclosure. Forexample, FIG. 1 illustrates an example of a light-emitting element LDthat can be used as a light source of a pixel in accordance with one ormore embodiments of the present disclosure, and FIG. 2 illustrates anexample of a section of the light-emitting element LD, which correspondsto the line I-I′ shown in FIG. 1 .

Referring to FIGS. 1 and 2 , the light-emitting element LD may include afirst semiconductor layer SCL1, an active layer ACT (also referred to asa “light-emitting layer”), and a second semiconductor layer SCL2, whichare sequentially located and/or stacked along one direction (e.g., alength direction), and an insulative film INF surrounding outercircumferential surfaces (e.g., side surfaces) of the firstsemiconductor layer SCL1, the active layer ACT, and the secondsemiconductor layer SCL2. In one or more embodiments, the light-emittingelement LD may further include an electrode layer ETL located on thesecond semiconductor layer SCL2. The insulative film INF may at leastpartially surround an outer circumferential surface of the electrodelayer ETL or may not surround the outer circumferential surface of theelectrode layer ETL. In some embodiments, the light-emitting element LDmay further include another electrode layer located on one surface(e.g., a lower surface) of the first semiconductor layer SCL1.

In one or more embodiments, the light-emitting element LD may beprovided in a rod shape. In description of one or more embodiments ofthe present disclosure, the rod shape may include various forms ofrod-like shape or bar-like shape, including a circular pillar shape, apolygonal pillar shape, and the like, and the shape of a section of therod shape is not particularly limited. In one or more embodiments, alength L of the light-emitting element LD may be greater than a diameterD (or a width of a cross-section) of the light-emitting element LD.

The light-emitting element LD may include a first end portion EP1 and asecond end portion EP2. In one or more embodiments, the first endportion EP1 and the second end portion EP2 may face each other. Forexample, the light-emitting element LD may include the first end portionEP1 and the second end portion EP2 at respective ends thereof in thelength direction (or thickness direction). The first end portion EP1 ofthe light-emitting element LD may include a first base surface (e.g., anupper surface) of the light-emitting element LD and/or a peripheral areathereof. The second end portion EP2 of the light-emitting element LD mayinclude a second base surface (e.g., a lower surface) of thelight-emitting element LD and/or a peripheral area thereof.

The first semiconductor layer SCL1, the active layer ACT, the secondsemiconductor layer SCL2, and the electrode layer ETL may besequentially located in a direction from the second end portion EP2 tothe first end portion EP1 of the light-emitting element LD. For example,the electrode layer ETL (or the second semiconductor layer SCL2) may belocated at the first end portion EP1 of the light-emitting element LD,and the first semiconductor layer SCL1 (or another electrode layer thatis adjacent to the first semiconductor layer SCL1 and is electricallyconnected to the first semiconductor layer SCL1) may be located at thesecond end portion EP2 of the light-emitting element LD.

The first semiconductor layer SCL1 may include a first conductivity typesemiconductor layer including a first conductivity type dopant. Forexample, the first semiconductor layer SCL1 may be an N-typesemiconductor layer including an N-type dopant.

In one or more embodiments, the first semiconductor layer SCL1 mayinclude a nitride-based semiconductor material or a phosphide-basedsemiconductor material. In one or more embodiments, the firstsemiconductor layer SCL1 may include a nitride-based semiconductormaterial including at least one material among GaN, AlGaN, InGaN,AlInGaN, AlN, and InN, or a phosphide-based semiconductor materialincluding at least one material among GaP, GaInP, AlGaP, AlGaInP, AIP,and InP. In one or more embodiments, the first semiconductor layer SCL1may include an N-type dopant such as Si, Ge or Sn. The firstsemiconductor layer SCL1 may be formed by using another material inaddition to the aforementioned materials.

The active layer ACT may be located on the first semiconductor layerSCL1. The active layer ACT may include a single- or multi-quantum well(QW) structure. When a voltage that is a threshold voltage or higher isapplied across both ends of the light-emitting element LD, electron-holepairs may be combined in the active layer ACT, and accordingly, lightcan be emitted in the light-emitting element LD.

In one or more embodiments, the active layer ACT may emit light having avisible light wavelength band (e.g., light having a wavelength of about400 nm to about 900 nm). For example, the active layer ACT may emitlight of blue, which has a wavelength in a range of about 450 nm toabout 480 nm, light of green, which has a wavelength in a range of about480 nm to about 500 nm, or light of red, which has a wavelength in arange of about 620 nm to about 750 nm. The active layer ACT may emitlight of another color and/or another wavelength band in addition to theaforementioned color and/or the aforementioned wavelength band.

In some embodiments, the active layer ACT may include a nitride-basedsemiconductor material or a phosphide-based semiconductor material. Inone or more embodiments, the active layer ACT may include anitride-based semiconductor material including at least one materialamong GaN, AlGaN, InGaN, InGaAlN, AIN, InN, and AlInN, or aphosphide-based semiconductor material including at least one materialamong GaP, GaInP, AlGaP, AlGaInP, AIP, and InP. The materialconstituting the emitting layer EML is not limited thereto. The activelayer ACT may be formed by using another material in addition to theaforementioned materials.

The second semiconductor layer SCL2 may be located on the active layerACT. The second semiconductor layer SCL2 may include a secondconductivity type semiconductor layer including a second conductivitytype dopant. For example, the second semiconductor layer SCL2 may be aP-type semiconductor layer including a P-type dopant.

In one or more embodiments, the second semiconductor layer SCL2 mayinclude a nitride-based semiconductor material or a phosphide-basedsemiconductor material. In one or more embodiments, the secondsemiconductor layer SCL2 may include a nitride-based semiconductormaterial including at least one material among GaN, AlGaN, InGaN,AlInGaN, AlN, and InN, or a phosphide-based semiconductor materialincluding at least one material among GaP, GaInP, AlGaP, AlGaInP, AIP,and InP. In one or more embodiments, the second semiconductor layer SCL2may include a P-type dopant such as Mg. The second semiconductor layerSCL2 may be formed by using another material in addition to theaforementioned materials.

In one or more embodiments, the first semiconductor layer SCL1 and thesecond semiconductor layer SCL2 include the same semiconductor material,and may include dopants of different conductivity types. In one or moreother embodiments, the first semiconductor layer SCL1 and the secondsemiconductor layer SCL2 include different semiconductor materials, andmay include dopants of different conductivity types.

In one or more embodiments, the first semiconductor layer SCL1 and thesecond semiconductor layer SCL2 may have different length (or differentthicknesses) in the length direction of the light-emitting element LD.In one or more embodiments, the first semiconductor layer SCL1 may havea length (or thickness) that is longer (or thicker) than a length (orthickness) of the second semiconductor layer SCL2 along the lengthdirection of the light-emitting element LD. Accordingly, the activelayer ACT may be located closer to the first end portion EP1 (e.g., aP-type end portion) than the second end portion EP2 (e.g., an N-type endportion).

The electrode layer ETL may be located on the second semiconductor layerSCL2. The electrode layer ETL may be an electrode for protecting thesecond semiconductor layer SCL2, and for smoothly connecting the secondsemiconductor layer SCL2 to at least one circuit element, at least oneelectrode, and/or at least one line. For example, the electrode layerETL may be an ohmic contact electrode or a Schottky contact electrode.

In some embodiments, the electrode layer ETL may include a metal ormetal oxide. In one or more embodiments, the electrode layer ELT may beformed of one or mixture of a metal such as chromium (Cr), titanium(Ti), aluminum (Al), gold (Au), nickel (Ni) or copper (Cu), any oxide oralloy thereof, a transparent conductive material such as indium tinoxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zincoxide (ZnO) or indium oxide (In₂O₃), and the like. The electrode layerETL may be formed by using another conductive material in addition tothe aforementioned materials.

In some embodiments, the electrode layer ETL may be substantiallytransparent. Accordingly, light generated in the light-emitting elementLD can be transmitted through the electrode layer ETL.

The insulative film INF may be provided on a surface of thelight-emitting element LD to surround side surfaces of the firstsemiconductor layer SCL1, the active layer ACT, the second semiconductorlayer SCL2, and/or the electrode layer ETL.

Accordingly, the electrical stability of the light-emitting element LDcan be ensured, and the likelihood of a short-circuit defect through thelight-emitting element LD can be reduced or prevented.

The insulative film INF may expose the electrode layer ETL (or thesecond semiconductor layer SCL2) and the first semiconductor layer SCL1(or another electrode layer provided at the second end portion EP2 ofthe light-emitting element LD) at the first end portion EP1 and thesecond end portion EP2 of the light-emitting element LD, respectively.For example, the insulative film INF may be omitted from two basesurfaces (e.g., upper and lower surfaces of the light-emitting elementLD) corresponding to the first and second end portions EP1 and EP2 ofthe light-emitting element LD. Accordingly, each of the first endportion EP1 and the second end portion EP2 of the light-emitting elementLD is connected to at least one electrode, at least one line, and/or atleast one conductive pattern, to thereby apply an electrical signal(e.g., a driving signal and/or a power voltage) to the light-emittingelement LD.

When the insulative film INF is provided on the surface of thelight-emitting element LD, a surface defect of the light-emittingelement LD is reduced or minimized, thereby improving the lifetime andefficiency of the light-emitting element LD. In addition, the likelihoodof a short-circuit defect between light-emitting elements can be reducedor prevented even when the light-emitting elements LD are adjacent toeach other.

In one or more embodiments, the light-emitting element LD may bemanufactured through a surface treatment process. For example, thelight-emitting element LD may be surface-treated by using a hydrophobicmaterial. Accordingly, when a plurality of light-emitting elements LDare mixed in a liquid solution (or solvent) to be supplied to eachemission area (e.g., an emission area of each pixel and/or eachsub-pixel), the light-emitting elements LD are not unequally condensedin the solution but equally dispersed in the solution.

The insulative film INF may include a transparent insulating material.

Accordingly, light generated in the active layer ACT can be transmittedthrough the insulative film INF. For example, the insulative film INFmay include at least one insulating material among silicon oxide(SiO_(x)) (e.g., SiO₂), silicon nitride (SiN_(x)) (e.g., Si₃N₄),aluminum oxide (Al_(x)O_(y)) (e.g., Al₂O₃), and titanium oxide(Ti_(x)O_(y)) (e.g., TiO₂). The insulative film INF may be formed byusing another insulating material in addition to the aforementionedmaterial.

The insulative film INF may be single layer or a multilayer. In one ormore embodiments, the insulative film INF may be configured as a doublelayer.

In one or more embodiments, the insulative film INF may be partiallyetched (or removed) at a portion corresponding to at least one of thefirst end portion EP1 and the second end portion EP2 of thelight-emitting element LD. In one or more embodiments, the insulativefilm INF may be etched to be inclined at the first end portion EP1 ofthe light-emitting element LD.

In one or more embodiments, the light-emitting element LD may have asmall size in a range of nanometers to micrometers. For example, thelight-emitting element LD may have a diameter D (or a width of across-section) in the range of nanometers to micrometers. In one or moreembodiments, may have a diameter D and/or a length L in a range of abouta few tens of nanometers to about a few tens of micrometers.

The structure, shape, size, and/or kind of the light-emitting element LDmay be changed in some embodiments. For example, the structure, shape,size, and/or kind of the light-emitting element LD may be variouslychanged according to design conditions of a light-emitting device usingthe light-emitting element LD, light emission characteristics to besecured, or the like.

A light-emitting device including the light-emitting element LD may beused in various kinds of devices that require a light source. Forexample, light-emitting elements LD may be located in a pixel of adisplay device, and may be used as a light source of the pixel. Thelight-emitting element LD may be used in other types of devices thatrequire a light source, such as a lighting device.

FIG. 3 is a plan view illustrating a display device DD in accordancewith one or more embodiments of the present disclosure.

Referring to FIG. 3 , the display device DD may include a display panelDPN including pixels PXL, and at least one driving circuit DIC connectedto the display panel DPN. In one or more embodiments, the display deviceDD may include two or more driving circuits DIC.

The display panel DPN may include a display area DA in which the pixelsPXL are located, and a non-display area NA located at the periphery ofthe display area DA. Lines and/or pads, which are electrically connectedto the pixels PXL may be located in the non-display area NA. In one ormore embodiments, the non-display area NA may be located at an edge ofthe display panel DPN, and may surround the display area DA.

The pixels PXL may be arranged in the display area DA along at least onedirection. For example, the pixels PXL may be regularly arranged in thedisplay area DA along a first direction DR1 and a second direction DR2.In one or more embodiments, the first direction DR1 may be a horizontaldirection (or lateral direction) of the display area DA, and the seconddirection DR2 may be a vertical direction (or longitudinal direction) ofthe display area DA. The arrangement structure and/or arrangementdirection of the pixels PXL may be changed in some embodiments.

Each pixel PXL (also referred to as a “unit pixel”) may include asub-pixel (e.g., a sub-pixel SPX shown in FIG. 4 or 5 ). For example,each pixel PXL may include two or more sub-pixels SPX for emittinglights of different colors.

The driving circuit DIC (e.g., a driving integrated circuit) may belocated on a pad area PA of the display panel DPN. For example, thedriving circuit DIC may be located on the pad area PA of the displaypanel DPN in a third direction DR3 (e.g., a thickness or heightdirection of the display device DD) crossing the first direction DR1 andthe second direction DR2. The driving circuit DIC may be electricallyconnected to pads provided in the pad area PA, and may supply drivingsignals to the display panel DPN through the pads.

The driving circuit DIC may include a circuit board CB and an integratedcircuit IC. The circuit board CB may be a flexible print circuit board(FPCB), a polymer film, or another type of substrate or film. In one ormore embodiments, the driving circuit DIC may be attached onto the padarea PA in the form of a tape automated bonding (TAB)-IC. The TAB-IC mayinclude a tape carrier package (TCP) obtained by mounting an integratedcircuit (IC) in a chip form on a polymer film and a chip on film (COF)obtained by mounting an integrated circuit IC in a chip form on aflexible printed circuit board. The driving circuit DIC may be providedin another form or another structure.

The integrated circuit IC may include a driver for driving the pixelsPXL. For example, the driving circuit DIC may include a scan driver(also referred to as a “gate driver”) for supplying scan signals and/orcontrol signals to scan lines and/or control lines of pixels PXL (orsub-pixels SPX constituting the pixels PXL), and a data driver (alsoreferred to as a “source driver”) for supplying data signals to datalines of the pixels PXL. In one or more other embodiments, at least aportion of the scan driver and/or the data driver may be provided and/orformed in the display panel DPN, or may be mounted on another board orthe like to be connected to the display panel DPN. In one or moreembodiments, the data driver may include a sensing circuit for sensingcharacteristics of the pixels PXL. In one or more other embodiments, thedisplay device DD may include a separate sensing circuit separated fromthe data driver.

In one or more embodiments, the display panel DPN may be partitionedinto two or more parts or areas, and the display device DD may includetwo or more driving circuits DIC corresponding the respective parts orareas. Each driving circuit DIC may be electrically connected to pixelsPXL located in a corresponding part or area, to supply driving signalsto the pixels PXL.

The display device DD may further include an additional component. Forexample, the display device DD may further include a timing controllerelectrically connected to the integrated circuit IC and a power voltagegenerator electrically connected to the pixels PXL and the integratedcircuits IC. In one or more embodiments, the timing controller and thepower voltage generator may be mounted and/or formed on a separatedcircuit board electrically connected to the driving circuits DIC, butembodiments are not limited thereto.

In one or more embodiments, the driving circuits DIC may be located ononly one edge area of the display panel DPN to be adjacent to any oneside of the display area DA. For example, the driving circuits DIC maybe located only on one portion (e.g., a portion corresponding to the padareas PA and a peripheral area thereof) of the non-display area NA,which corresponds to a bottom edge area (or top edge area) of thedisplay panel DPN. The display device DD may be a single side drivingdisplay device in which driving signals are supplied to the displaypanel DPN through pads located in a bottom edge area (or top edge area)of the display panel DPN and through driving circuits DIC electricallyconnected to the pads.

In the case of the single side driving display device, the drivingcircuits DIC (or the pads connected to the driving circuits DIC) may notbe located on the other areas (e.g., a top end edge area, a left edgearea, and/or a right edge area of the display panel DPN) in contact withother sides of the display area DA in the non-display area NA of thedisplay panel DPN. Accordingly, in the other areas of the non-displayarea NA, the width and/or area of the non-display area NA can be reducedor minimized.

FIGS. 4 and 5 are circuit diagrams illustrating sub-pixels SPX inaccordance with embodiments of the present disclosure. For example,FIGS. 4 and 5 illustrate sub-pixels SPX including light-emitting unitsEMU having different structures.

The sub-pixel SPX shown in FIG. 4 or 5 may be one of the sub-pixels SPXlocated in the display area DA shown in FIG. 3 . The sub-pixels SPXlocated in the display area DA may have structures substantiallyidentical or similar to each other.

Referring to FIGS. 4 and 5 , the sub-pixel SPX may be connected to ascan line SL, a data line DL, a first power line PL1, and a second powerline PL2. In one or more embodiments, the sub-pixel SPX may be furtherconnected to another power line and/or another signal line. For example,the sub-pixel SPX may be further connected to a sensing line SENL (alsoreferred to as an “initialization power line”) and/or a control lineSSL.

The sub-pixel SPX may include a light-emitting unit EMU for generatinglight with a luminance corresponding to each data signal. Also, thesub-pixel SPX may further include a pixel circuit PXC for driving thelight-emitting unit EMU.

The pixel circuit PXC may be connected to the scan line SL and the dataline DL, and may be connected between the first power line PL1 and thelight-emitting unit EMU. For example, the pixel circuit PXC may beelectrically connected to the scan line SL to which a scan signal issupplied, the data line DL to which a data signal is supplied, the firstpower line PL1 to which a first power voltage VDD is applied, and thelight-emitting unit EMU.

The pixel circuit PXC may be selectively further connected to thecontrol line SSL to which a control signal is supplied, and the sensingline SENL connected to a reference power source (or initialization powersource) or to a sensing circuit, respectively corresponding to a displayperiod or a sensing period. In one or more embodiments, the scan signaland the control signal, which are supplied to the sub-pixel SPX, (e.g.,a scan signal and a control signal, which are supplied to sub-pixels SPXand/or pixels PXL of a corresponding horizontal line) may be identicalto or different from each other. In one or more embodiments, when thescan signal and the control signal of the sub-pixel SPX are the samesignal, the scan line SL and the control line SSL, which are connectedto the sub-pixel SPX, may be integrated.

The pixel circuit PXC may include at least one transistor and acapacitor. For example, the pixel circuit PXC may include a firsttransistor M1, a second transistor M2, a third transistor M3, and astorage capacitor Cst.

The first transistor M1 may be electrically connected between the firstpower line PL1 and a second node N2. The second node N2 may be a node atwhich the pixel circuit PXC and the light-emitting unit EMU areconnected to each other. For example, the second node N2 may be a nodeat which one electrode (e.g., a source electrode) of the firsttransistor M1 and the light-emitting unit EMU are electrically connectedto each other. A gate electrode of the first transistor M1 may beelectrically connected to a first node N1. The first transistor M1 maycontrol a driving current supplied to the light-emitting unit EMUcorresponding to a voltage of the first node N1. For example, the firsttransistor M1 may be a driving transistor of the sub-pixel SPX.

In one or more embodiments, the first transistor M1 may further includea bottom metal layer BML (also referred to as a “back-gate electrode” ora “second gate electrode”). In one or more embodiments, the bottom metallayer BML may be electrically connected to the one electrode (e.g., thesource electrode) of the first transistor M1.

In one or more embodiments in which the first transistor M1 includes thebottom metal layer BML, a back-biasing technique (or sync technique) maybe applied, wherein a threshold voltage of the first transistor M1 ismoved in a negative direction or positive direction by applying aback-biasing voltage to the bottom metal layer BML of the firsttransistor M1. In addition, when the bottom metal layer BML is locatedon the bottom of a semiconductor pattern (e.g., a semiconductor patternSCP shown in FIG. 7 ) constituting a channel of the first transistor M1,light incident onto the semiconductor pattern may be blocked, therebystabilizing an operating characteristic of the first transistor M1.

The second transistor M2 may be electrically connected between the dataline DL and the first node N1. In addition, a gate electrode of thesecond transistor M2 may be electrically connected to the scan line SL.The second transistor M2 may be turned on when a scan signal having agate-on voltage (e.g., a logic high voltage or high level voltage) issupplied from the scan line SL to electrically connect the data line DLand the first node N1.

A data signal of a corresponding frame may be supplied to the data lineDL for each frame period. The data signal may be transferred to thefirst node N1 through the second transistor M2 during a period in whichthe scan signal having the gate-on voltage is supplied. For example, thesecond transistor M2 may be a switching transistor for transferring eachdata signal to the inside of the sub-pixel SPX.

The capacitor Cst may be electrically connected between the first nodeN1 and the second node N2. The capacitor Cst may charge a voltagecorresponding to the data signal supplied to the first node N1 duringeach frame period.

The third transistor M3 may be electrically connected between the secondnode N2 and the sensing line SENL. In addition, a gate electrode of thethird transistor M3 may be electrically connected to the control lineSSL (or the scan line SL). The third transistor M3 may be turned on whena control signal (or the scan signal) having the gate-on voltage (e.g.,the logic high voltage or high level voltage) is supplied from thecontrol line SSL to transfer a reference voltage (or initializationvoltage) supplied via the sensing line SENL to the second node N2, or totransfer a voltage of the second node N2 to the sensing line SENL. Inone or more embodiments, the voltage of the second node N2 may betransferred to the sensing circuit through the sensing line SENL, and acharacteristic deviation and/or a change of sub-pixels SPX may becompensated based on a sensing signal output from the sensing circuit.

Although a case where the transistors M included in the pixel circuitPXC are all N-type transistors is illustrated in FIGS. 4 and 5 ,embodiments are not limited thereto. For example, at least one of thefirst, second, and third transistors M1, M2, and M3 may be changed to aP-type transistor. The structure and driving method of the sub-pixel SPXmay be variously changed in some embodiments.

The light-emitting unit EMU may include at least one light-emittingelement LD connected between the first power line PL1 and the secondpower line PL2. In one or more embodiments, the light-emitting elementLD may include a first end portion EP1 electrically connected to thefirst power line PL1 through the pixel circuit PXC and a second endportion EP2 electrically connected to the second power line PL2.

The first power voltage VDD and a second power voltage VSS may besupplied to the light-emitting unit EMU respectively through the firstpower line PL1 and the second power line PL2. For example, thelight-emitting unit EMU may be electrically connected to a power voltagegenerator through the first power line PL1 and the second power linePL2, and the first power voltage VDD and the second power voltage VSS,which are generated by the power voltage generator, may be supplied tothe light-emitting unit EMU through the first power line PL1 and thesecond power line PL2, respectively. In one or more embodiments, thefirst power voltage VDD may be a high-potential power voltage, and thesecond power voltage VSS may be a low-potential power voltage.

In one or more embodiments, the first end portion EP1 of thelight-emitting element LD may be a P-type end portion, and the secondend portion EP2 of the light-emitting element LD may be an N-type endportion. For example, the light-emitting element LD may be connected ina forward direction between the first power line PL1 and the secondpower line PL2. Accordingly, the light-emitting element LD canconstitute an effective light source of a corresponding sub-pixel SPX.

In one or more embodiments, as shown in FIG. 4 , the light-emitting unitEMU may include a single light-emitting element LD connected in theforward direction between the first power line PL1 and the second powerline PL2 (e.g., between the pixel circuit PXC and the second power linePL2). In one or more other embodiments, the light-emitting unit EMU mayinclude two or more light-emitting elements LD connected in the forwarddirection between the first power line PL1 and the second power linePL2. For example, as shown in FIG. 5 , the light-emitting unit EMU mayinclude light-emitting elements LD connected in series-parallel to eachother between the first power line PL1 and the second power line PL2. Inone or more embodiments, the light-emitting unit EMU may include firstand second serial stages, and may include at least one firstlight-emitting element LD1 located and/or connected in the first serialstage and at least one second light-emitting element LD2 located and/orconnected in the second serial stage. The connection structure oflight-emitting elements LD constituting each light-emitting unit EMU maybe changed in some embodiments. For example, the light-emitting elementsLD may be connected only in series or in parallel to each other betweenthe first power line PL1 and the second power line PL2. The number,kind, and/or connection structure of a light-emitting element(s)constituting the effective light source of the sub-pixel SPX may bevariously changed in some embodiments.

In one or more embodiments, each light-emitting element LD may be arod-shaped inorganic light-emitting element. Also, each light-emittingelement LD may be a subminiature light-emitting element having a size ina range of nanometers to micrometers. In one or more embodiments, thelight-emitting element LD may be a light-emitting element LD in the oneor more embodiments corresponding to FIGS. 1 and 2 , but embodiments arenot limited thereto. For example, the kind, material, structure, size,and/or shape of the light-emitting element LD may be variously changedin some embodiments.

FIG. 6 is a plan view illustrating a display area DA in accordance withone or more embodiments of the present disclosure. In FIG. 6 , based ona first pixel PXL1 and a second pixel PXL2, which are adjacent to eachother along the second direction DR2 in the display area DA, the displayarea DA and a structure of pixels PXL located in the display area DAwill be schematically illustrated. For example, the first pixel PXL1 maybe located on an nth (n is a natural number) horizontal line (e.g., annth pixel row) and an mth (m is a natural number) vertical line (e.g.,an mth pixel column) of the display area DA, and the second pixel PXL2may be located on an (n+1)th horizontal line (e.g., an (n+1)th pixelrow) and the mth vertical line of the display area DA. The first pixelPXL1 and the second pixel PXL2 may be located on the same vertical linein the display area DA, and may be vertically adjacent to each other inthe second direction DR2.

Referring to FIGS. 3 to 6 , the display area DA may include pixels PXLincluding the first pixel PXL1 and the second pixel PXL2, and scan linesSL, data lines DL, sensing lines SENL, a first power line PL1, and asecond power line PL2, which are electrically connected to the pixelsPXL. In one or more embodiments, a control line SSL of each horizontalline may be integrated with a scan line SL of the correspondinghorizontal line.

In one or more embodiments, the display area DA may further includeconnection lines crossing the scan lines SL and/or at least one dummyline. For example, the display area DA may include connection lines CLcorresponding to the respective scan lines SL, and may selectivelyfurther include a dummy line and the like.

In one or more embodiments, connection lines CL each electricallyconnected to any one scan line SL and/or dummy lines separated from theconnection lines CL may be located inside some pixel columns among pixelcolumns of the display area DA and/or at the periphery thereof. In oneor more embodiments, the dummy lines may be used as sub-lines forreducing a resistance of the first power line PL1 and/or the secondpower line PL2. Dummy lines (or sub-power lines) each electricallyconnected to the first power line PL1 or the second power line PL2 maybe located inside other pixel columns and/or at the periphery thereof.

The scan lines SL may extend in the first direction DR1 in the displayarea DA, and may be formed for every horizontal line. For example, thescan lines SL may include an nth scan line SLn located on the nthhorizontal line of the display area DA or at the periphery thereof, andmay include an (n+1)th scan line SLn+1 located on the (n+1)th horizontalline of the display area DA or at the periphery thereof. Each scan lineSL may extend in the first direction DR1 in the display area DA, and maybe electrically connected to pixel circuits PXC of sub-pixels SPXlocated on a corresponding horizontal line.

In one or more embodiments, each scan line SL may be electricallyconnected to at least one connection line CL, and may be electricallyconnected to a driving circuit DIC through the at least one connectionline CL. For example, the nth scan line SLn may be electricallyconnected to an nth connection line CLn, and may be electricallyconnected to a driving circuit DIC through the nth connection line CLnand through a pad electrically connected thereto. Similarly, the (n+1)thscan line SLn+1 may be electrically connected to an (n+1)th connectionline CLn+1, and may be electrically connected to a driving circuit DICthrough the (n+1)th connection line CLn+1 and through a pad electricallyconnected thereto.

The connection lines CL may extend in the second direction DR2 in thedisplay area DA, and may be formed on at least some vertical lines or atthe periphery thereof. The connection lines CL may correspond to therespective scan lines SL, and may be electrically connected to therespective scan lines SL. For example, the connection lines CL mayinclude the nth connection line CLn electrically connected to the nthscan line SLn, and the (n+1)th connection line CLn+1 electricallyconnected to the (n+1)th scan line SLn+1. The positions, size (e.g.,width and/or length), and/or arrangement order of the connection linesCL may be changed in some embodiments.

The data lines DL may extend along the second direction DR2 in thedisplay area DA, and may be formed for every vertical line. For example,an mth data line DLm may be formed on the mth vertical line of thedisplay area DA. However, embodiments are not limited thereto. Forexample, the data lines DL may be formed for every two vertical linesadjacent to each other, and the two vertical lines may share data linesDL. Scan lines SL connected to pixels PXL of the two vertical lines areseparated from each other, so that a time for which a data signal isinput to the pixels PXL can be divided.

Each data line DL may be connected to pixel circuits PXC of sub-pixelsSPX located on a corresponding vertical line. Also, each data line DLmay include sub-data lines individually connected to sub-pixels SPXconstituting each pixel PXL. For example, the mth data line DLm mayinclude a first sub-data line D1 electrically connected to firstsub-pixels SPX1 of pixels PXL located on the mth vertical line, a secondsub-data D2 electrically connected to second sub-pixels SPX2 of thepixels PXL located on the mth vertical line, and a third sub-data lineD3 electrically connected to third sub-pixels SPX3 of the pixels PXLlocated on the mth vertical line. Accordingly, a data signal can beindividually supplied to each sub-pixel SPX.

The sensing line SENL may extend along the second direction DR2, and maybe formed for every at least one vertical line. In one or moreembodiments, the sensing lines SENL may be formed for every verticalline, and may be commonly connected to sub-pixels SPX constituting eachpixel PXL. A characteristic of each pixel PXL may be individuallydetected. In one or more other embodiments, the sensing lines SENL maybe formed such that a plurality of vertical lines share the sensinglines SENL. A characteristic of pixels PXL may be detected in a blockunit including a plurality of pixels PXL.

The first power line PL1 and the second power line PL2 may be commonlyconnected to the pixels PXL of the display area DA. For example, thefirst power line PL1 may be commonly connected to pixel circuits PXC ofsub-pixels SPX, and the second power line PL2 may be commonly connectedto a light-emitting unit EMU (e.g., second alignment electrodes ALE2 ofthe light-emitting units EMU) of the sub-pixels SPX.

In one or more embodiments, each of the first power line PL1 and thesecond power line PL2 may be formed as a line having a mesh shape.Accordingly, a voltage drop (IR drop) of the first power voltage VDD andthe second power voltage VSS can be prevented or reduced, and the firstpower voltage VDD and the second power voltage VSS, which respectivelyhave a uniform level, can be transferred to the pixels PXL.

For example, the first power line PL1 may include at least one firsthorizontal power line HPL1 (also referred to as a “first lateral powerline”) extending in the first direction DR1 in the display area DA, andat least one first vertical power line VPL1 (also referred to as a“first longitudinal power line”) that extends in the second directionDR2 in the display area and is electrically connected to the firsthorizontal power line HPL1. The at least one first horizontal power lineHPL1 and the at least one first vertical power line VPL1 may cross eachother, and may be connected to each other at all or some crossingpoints.

Similarly, the second power line PL2 may include at least one secondhorizontal power line HPL2 (also referred to as a “second lateral powerline”) extending in the first direction DR1 in the display area DA, andat least one second vertical power line VPL2 (also referred to as a“second longitudinal power line”) that extends in the second directionDR2 in the display area and that is electrically connected to the secondhorizontal power line HPL2. The at least one second horizontal powerline HPL2 and the at least one second vertical power line VPL2 may crosseach other, and may be connected to each other at all or some crossingpoints.

In one or more embodiments, the first horizontal power line HPL1 and thesecond horizontal power line HPL2 may be formed for every one horizontalline or once for each of respective pluralities of horizontal lines. Forexample, the first horizontal power line HPL1 and the second horizontalpower line HPL2 may be alternately arranged for every horizontal line.In one or more embodiments, the first horizontal power line HPL1 may belocated on odd-numbered horizontal lines (or even-numbered horizontallines), and the second horizontal power line HPL2 may be located oneven-numbered horizontal lines (or odd-numbered horizontal lines).

In one or more embodiments, the first horizontal power line HPL1 and thesecond horizontal power line HPL2 may be immediately adjacent toemission areas (e.g., emission areas corresponding to respectivelight-emitting units EMU) provided in pixels PXL of a correspondinghorizontal line. For example, the first horizontal power line HPL1 andthe second horizontal power line HPL2 may be immediately adjacent tobottom edge areas of emission areas corresponding to light-emittingunits EMU of the corresponding horizontal line, and may traverse pixelareas PXA in which the pixels of the corresponding horizontal line arelocated. In one or more embodiments, the first horizontal power lineHPL1 may be located between second and third pixel circuits PXC2 andPXC3 (e.g., pixel circuits of second and third sub-pixels SPX2 and SPX3)that are provided in pixels PXL of odd-numbered horizontal lines (oreven-numbered horizontal lines), and the second horizontal power lineHPL2 may be located between second and third pixel circuits PXC2 andPXC3 (pixel circuits of second and third sub-pixels SPX2 and SPX3) thatare provided in pixels PXL of even-numbered horizontal lines (orodd-numbered horizontal lines). In one or more embodiments, first andthird pixels PXC1 and PXC3 (pixel circuits of first and third sub-pixelsSPX1 and SPX3) of pixels PXL provided on each horizontal line may belocated between two lines that each extend in the first direction andare located at respective sides of emission areas corresponding tolight-emitting units EMU of corresponding horizontal lines in the seconddirection DR2. In one or more embodiments, the first and third pixelcircuits PXC1 and PXC3 provided in the pixels PXL of each horizontalline may be located between a scan line SL of the correspondinghorizontal line and the first or second horizontal power line HPL1 orHPL2.

The number, positions, and/or arrangement structure of first and secondhorizontal power lines HPL1 and HPL2 may be variously changed in someembodiments.

In one or more embodiments, the first vertical power line VPL1 and thesecond vertical power line VPL2 may be formed for every at least onevertical line. For example, the first vertical power line VPL1 and thesecond vertical power line VPL2 may be formed for every vertical line(e.g., at the periphery thereof), and may be spaced apart from eachother with pixel circuits PXC arranged on a pixel column of acorresponding vertical line, which are interposed therebetween. Thenumber and/or positions of first and second vertical power lines VPL1and VPL2 may be various changed in some embodiments.

Each pixel PXL may include sub-pixels SPX. In one or more embodiments,each pixel PXL may include a first sub-pixel SPX1, a second sub-pixelSPX2, and a third sub-pixel SPX3.

Each sub-pixel SPX may include a pixel circuit PXC and a light-emittingunit EMU. For example, the first sub-pixel SPX1 may include a firstpixel circuit PXC1 and a first light-emitting unit EMU1, and the secondsub-pixel SPX2 may include a second pixel circuit PXC2 and a secondlight-emitting unit EMU2. The third sub-pixel SPX3 may include a thirdpixel circuit PXC3 and a third light-emitting unit EMU3.

Pixel circuits PXC and light-emitting units EMU of each pixel PXL may belocated in different layers, and may overlap with each other. Forexample, the pixel circuits PXC may be located in a circuit layer (e.g.,a pixel circuit PCL shown in FIG. 7 ) of a corresponding pixel area PXAin which each pixel PXL is located. The light-emitting units EMU may belocated in a display layer (e.g., a display layer DPL shown in FIG. 7 )of the corresponding pixel area PXA to overlap with at least one pixelcircuit PXC (e.g., the first light-emitting unit EMU1 may overlap thefirst pixel circuit PXC1 and the third pixel circuit PXC3) among thepixel circuits PXC of the corresponding pixel PXL, and/or to overlap atleast one line (e.g., at least one scan line SL, a sensing line SENL, adata line, a first power line PL1, a second power line PL2, and/or aconnection line CL).

In FIG. 6 , an area in which each pixel circuit PXC is located will bedisplayed based on an area in which main circuit elements (e.g.,transistors M and a capacitor Cst), which constitute each pixel circuitor at least a portion of the circuit elements, are located. In someembodiments, another of the circuit elements may be located outside ofthe displayed area. Also, in FIG. 6 , an area in which eachlight-emitting unit EMU is located will be displayed based on an area inwhich main components (e.g., light-emitting elements LD electrodeselectrically connected to the light-emitting elements LD) constitutingeach light-emitting unit EMU, or based on each emission area in which atleast a portion of the main components is located. In some embodiments,at least another portion of the main elements (e.g. end portions ofelectrodes connected to the light-emitting elements LD) may be locatedat the outside of the display area.

The first, second, and third pixel circuits PXC1, PXC2, and PXC3 may bearranged in the second direction DR2 in each pixel area PXA. Forexample, the first, second, and third pixel circuits PXC1, PXC2, andPXC3 of the first pixel PXL1 may be arranged along the second directionDR2 in an order (e.g., a predetermined order) in a first pixel area PXA1in which the first pixel PXL1 is provided. Similarly, the first, second,and third pixel circuits PXC1, PXC2, and PXC3 of the second pixel PXL2may be arranged along the second direction DR2 in an order (e.g., apredetermined order) in a second pixel area PXA2 in which the secondpixel PXL2 is provided.

In one or more embodiments, the third pixel circuit PXC3 may be locatedat the center of each pixel area PXA with respect to the seconddirection DR2, and the first and second pixel circuits PXC1 and PXC2 maybe located at respective sides of the third pixel circuit PXC3 in thesecond direction DR2. For example, in each pixel area PXA, pixelcircuits PXC may be arranged in an order of the first pixel circuitPXC1, the third pixel circuit PXC3, and the second pixel circuit PXC2along the second direction DR2. The locations and/or arrangement orderof the first, second, and third pixel circuits PXC1, PXC2, and PXC3 maybe changed in some embodiments.

The first, second, and third pixel circuits PXC1, PXC2, and PXC3 may becommonly connected to the first power line PL1 and a scan line SL of acorresponding horizontal line, and may be connected to differentsub-data lines of a corresponding vertical line. For example, the firstpixel circuit PXC1 may be electrically connected to a first sub-dataline D1, and the second pixel circuit PXC2 may be electrically connectedto a second sub-data line D2. The third sub-pixel circuit PXC3 may beelectrically connected to a third sub-data line D3.

In one or more embodiments, the first, second, and third pixel circuitsPXC1, PXC2, and PXC3 may be further connected to a sensing line SENL.For example, first, second, and third pixel circuits PXC1, PXC2, andPXC3 may be commonly connected to a sensing line SENL of thecorresponding vertical line.

The first, second, and third light-emitting units EMU1, EMU2, and EMU3may be connected between the respective pixel circuits PXC and thesecond power line PL2. For example, the first, second, and thirdlight-emitting units EMU1, EMU2, and EMU3 may be electrically connectedto the first, second, and third pixels PXC1, PXC2, and PXC3 throughfirst contact holes (e.g., first contact holes CH1 shown in FIGS. 8 and9 ), respectively. Also, the first, second, and third light-emittingunits EMU1, EMU2, and EMU3 may be electrically connected to the secondpower line PL2 respectively through second contact holes (e.g., secondcontact holes CH2 shown in FIGS. 8 and 9 ).

The first, second, and third light-emitting units EMU1, EMU2, and EMU3may be arranged in the first direction DR1 in each pixel area PXA. Forexample, first, second, and third light-emitting units EMU1, EMU2, andEMU3 of the first pixel PXL1 may be sequentially arranged along thefirst direction DR1 in a first pixel area PXA1 corresponding to thefirst pixel PXL1. Similarly, first, second, and third light-emittingunits EMU1, EMU2, and EMU3 of the second pixel PXL2 may be sequentiallyarranged along the first direction DR1 in a second pixel area PXA2corresponding to the second pixel PXL2. The first, second, and thirdsub-pixels SPX1, SPX2, and SPX3 may respectively have emission areas(e.g., first, second, and third emission areas EA1, EA2, and EA3 shownin FIG. 9 ) corresponding to respective areas (or one portions) of thefirst, second, and third light-emitting units EMU1, EMU2, and EMU3.Accordingly, the emission areas of the first, second, and thirdsub-pixels SPX1, SPX2, and SPX3 may be sequentially arranged along thesecond direction DR2. Therefore, it can be seen that, with respect tothe emission areas of the first, second, and third sub-pixels SPX1,SPX2, and SPX3, the first, second, and third sub-pixels SPX1, SPX2, andSPX3 are arranged along the second direction DR2.

Although one or more embodiments in which pixel circuits PXC andlight-emitting units EMU of sub-pixels SPX are arranged along differentdirections in each pixel area PXA has been disclosed in FIG. 6 ,embodiments are not limited thereto. For example, the positions and/orarrangement directions of the pixel circuits PXC and the light-emittingunits EMU may be variously changed in some embodiments.

FIG. 7 is a sectional view illustrating a display area DA in accordancewith one or more embodiments of the present disclosure. For example,FIG. 7 schematically illustrates a section of the display area DA, basedon one sub-pixel SPX including a light-emitting unit EMU having aseries-parallel structure (or serial structure) including first andsecond light-emitting elements LD1 and LD2 as shown in the one or moreembodiments corresponding to FIG. 5 .

Sub-pixels SPX located in the display area DA may have sectionalstructures substantially identical or similar to each other. However,the sizes, positions, and/or shapes of circuit elements constituting thesub-pixels SPX and electrodes included in the circuit elements may bedifferent from each other according to the sub-pixels SPX. For example,when viewed on a plane, a first transistor M1 of a first sub-pixel SPX1may have a shape and/or a size that is different from a shape and/or asize of a first transistor M1 of a second sub-pixel SPX2.

Referring to FIGS. 1 to 7 , the display device DD may include a baselayer BSL, a circuit layer PCL (also referred to as a “circuit elementlayer,” a “pixel circuit layer,” or a “backplane”), and a display layerDPL (also referred to as a “display element layer” or a “light-emittingelement layer”). The circuit layer PCL and the display layer DPL mayoverlap with each other on the base layer BSL. In one or moreembodiments, the circuit layer PCL and the display layer DPL may besequentially located on one surface of the base layer BSL.

The display device DD may further include a color filter layer CFLand/or an encapsulation layer ENC (or protective layer) located on(e.g., above) the display layer DPL. In one or more embodiments, thecolor filter layer CFL and the encapsulation layer ENC may be formeddirectly on the one surface of the base layer BSL on which the circuitlayer PCL and the display layer DPL are formed. Accordingly, thethickness of the display device DD can be reduced.

The base layer BSL may be a substrate or a film, which is made of arigid or flexible material. In one or more embodiments, the base layerBSL may include at least one insulating material, and may have asingle-layer structure or a multilayer structure.

The circuit layer PCL may be provided on the one surface of the baselayer BSL. The circuit layer PCL may include pixel circuits PXC of eachpixel PXL. For example, circuit elements (e.g., transistors M andcapacitors Cst) constituting first, second, and third pixel circuitsPXC1, PXC2, and PXC3 of a corresponding pixel PXL may be formed in eachpixel area PXA of the circuit layer PCL. In FIG. 7 , a section of anyone transistor M (e.g., a first transistor M1 including a bottom metallayer BML) provided in each pixel circuit PXC will be schematicallyillustrated as an example of circuit elements that may be located in thecircuit layer PCL of the display area DA.

Also, the circuit layer PCL may include signal lines and power lines,which are connected to the pixels PXL. For example, the circuit layerPCL may include scan lines SL, data lines DL, sensing lines SENL, afirst power line PL1, and a second power line PL2. In one or moreembodiments, the circuit layer PCL may further include connection linesCL and/or dummy lines.

In one or more embodiments, some lines (or portions of the lines)provided in the circuit layer PCL may be located in the same layer assome components or electrodes of transistors M. Other lines (or portionsof the lines) provided in the circuit layer PCL may be located in thesame layer as other components or electrodes of the transistors M.

The circuit layer PCL may include conductive layers includingelectrodes, conductive patterns and/or bridge patterns, and lines ofcircuit elements. For example, the circuit layer PCL may includeconductive layers (e.g., first, second, and third conductive layers)sequentially located on the base layer BSL along the third directionDR3. The conductive layers may respectively include electrodes,conductive patterns, bridge patterns, and/or lines. The circuit layerPCL may further include a semiconductor layer including semiconductorpatterns SCP of the transistors M.

The circuit layer PCL may further include insulating layers. Forexample, the circuit layer PCL may include a buffer layer BFL, a gateinsulating layer GI, an interlayer insulating layer ILD, and/or apassivation layer PSV, which are sequentially located on the one surfaceof the base layer BSL.

The circuit layer PCL may include a first conductive layer located onthe base layer BSL. In one or more embodiments, the first conductivelayer may be located between the base layer BSL and the buffer layerBFL, and may include bottom metal layers BML of first transistors M1included in the sub-pixels SPX. Each bottom metal layer BML may overlapwith a semiconductor pattern SCP of a first transistor correspondingthereto.

The first conductive layer may further include at least one line. Forexample, the first conductive layer may include lines (or portions ofthe lines) extending in the second direction DR2 in the display area DA.In one or more embodiments, the first conductive layer may include datalines DL, sensing lines SENL, first vertical power lines VPL1, secondvertical power lines VPL2, and/or connection lines CL.

The buffer layer BFL may be located on the one surface of the base layerBSL including the first conductive layer. The buffer layer BFL mayreduce or prevent the likelihood of an impurity being diffused into eachcircuit element.

A semiconductor layer may be located on the buffer layer BFL. Thesemiconductor layer may include semiconductor patterns SCP of thetransistors M. Each semiconductor pattern SCP may include a channelregion overlapping with a gate electrode GE of a correspondingtransistor M, and first and second conductive regions (e.g., source anddrain regions) located at respective sides of the channel region.

The gate insulating layer GI may be located on the semiconductor layer.A second conductive layer may be located on the gate insulating layerGI.

The second conductive layer may include gate electrodes GE of thetransistors M. The second conductive layer may further include oneelectrode (e.g., a lower electrode) of each of capacitors Cst providedin the pixel circuits PXC. Additionally, when at least one power line(e.g., a first vertical power line VPL1 and/or a second vertical powerline VPL2) and/or at least one signal line (e.g., connection lines CL),located in the display area DA, are/is configured as a multilayer, thesecond conductive layer may further include at least one conductivepattern (e.g., first sub-lines SLI1 shown in FIG. 8 ) constituting theat least one power line and/or the at least one signal line.

The interlayer insulating layer ILD may be located over the secondconductive layer. A third conductive layer may be located on theinterlayer insulating layer ILD.

The third conductive layer may include source electrodes SE and drainelectrodes DE of the transistors M. Each source electrode SE may berespectively connected to one region (e.g., the source region) of asemiconductor pattern SCP included in a corresponding transistor Mthrough at least one contact hole CH, and each drain electrode DE may beconnected to another area (e.g., the drain region) of the semiconductorpattern SCP included in the corresponding transistor M through at leastanother contact hole CH.

The third conductive layer may further include one electrode (e.g., anupper electrode) of each of the capacitors Cst provided in the pixelcircuits PXC, at least one line, and/or at least one bridge pattern. Forexample, the third conductive layer may include lines (or portions ofthe lines) extending in the first direction DR1 in the display area DA.In one or more embodiments, the third conductive layer may include scanlines SL, first horizontal power lines HPL1, and second horizontal powerlines HPL2. Additionally, when at least one power line (e.g., a firstvertical power line VPL1 and/or a second vertical power line VPL2)and/or at least one signal line (e.g., connection lines CL), which maybe located in the display area DA, are/is configured as a multilayer,the third conductive layer may further include at least one conductivepattern (e.g., second sub-lines SLI2 shown in FIG. 8 ) constituting theat least one power line and/or the at least one signal line.

Each of the electrodes, the conductive patterns, and/or the lines, whichconstitute the first to third conductive layers, may include aconductive material, thereby having conductivity, and the materialconstituting each of the conductive patterns, the electrodes, and/or thelines is not particularly limited. In one or more embodiments, each ofthe conductive patterns, the electrodes, and/or the lines, whichrespectively constitute the first to third conductive layers, mayinclude at least one metal selected from molybdenum (Mo), aluminum (Al),platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au),nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti),tantalum (Ta), tungsten (W), and copper (Cu). Besides, each of theconductive patterns, the electrodes, and/or the lines, whichrespectively constitute the first to third conductive layers, mayinclude various kinds of conductive materials.

The passivation layer PSV may be located over the third conductivelayer. Each of the buffer layer BFL, the gate insulating layer GI, theinterlayer insulating layer ILD, and the passivation layer PSV may beconfigured as a single layer or a multilayer, and may include aninorganic insulating material and/or an organic insulating material. Forexample, each of the buffer layer BFL, the gate insulating layer GI, theinterlayer insulating layer ILD, and the passivation layer PSV mayinclude silicon nitride (SiN_(x)), silicon oxide (SiO_(x)), siliconoxynitride (SiO_(x)N_(y)), or another insulating material. Although acase where the insulating layers of the circuit layer PCL (e.g., thebuffer layer BFL, the gate insulating layer GI, the interlayerinsulating layer ILD, and the passivation layer PSV) are substantiallyflat is illustrated in FIG. 7 , each insulating layer may have a bending(e.g., an uneven surface) corresponding to a step difference occurringdue to a lower conductive pattern and/or a lower insulating pattern.

In one or more embodiments, the passivation layer PSV may include anorganic insulating layer, and may substantially planarize a surface ofthe circuit layer PCL. However, the passivation layer PSV may have aslight bending corresponding to patterns (e.g., electrodes, conductivepatterns, and/or lines, which are included in the third conductivelayer) located thereunder. Accordingly, the passivation layer PSV mayhave a height difference caused by the lower patterns.

The display layer DPL may be located on the passivation layer PSV. Thedisplay layer DPL may include light-emitting units EMU of each pixelPXL. For example, light-emitting elements LD constituting first, second,and third light-emitting units EMU1, EMU2, and EMU3, and electrodesconnected thereto (e.g., at least one pair of alignment electrodes ALEand at least one pair of contact electrodes CNE, which are provided ineach light-emitting unit EMU), may be formed in each pixel area PXA ofthe display layer DPL.

In one or more embodiments, the display layer DPL may include a firstalignment electrode ALE1, a second alignment electrode ALE2, at leastone first light-emitting element LD1, a first contact electrode CNE1,and a second contact electrode CNE2, which are located in an emissionarea of each sub-pixel SPX to constitute a light-emitting unit EMU ofthe corresponding sub-pixel SPX. In one or more embodiments, eachlight-emitting unit EMU may further include a third alignment electrodeALE3, at least one second light-emitting element LD2, and a thirdcontact electrode CNE3, which are additionally provided in each emissionarea EA of the display layer DPL.

The display layer DPL may further include insulating layers and/orinsulating patterns, which are sequentially located on the one surfaceof the base layer BSL on which the circuit layer PCL is formed. Forexample, the display layer DPL may include bank patterns BNP, a firstinsulating layer INS1, a first bank BNK1, a second insulating layerINS3, and/or a fourth insulating layer INS4, which are sequentiallylocated on the circuit layer PCL. In one or more embodiments, thedisplay layer DPL may further include a second bank BNK2 and a lightconversion layer CCL.

The bank patterns BNP (also referred to as “patterns” or “wallpatterns”) may be provided and/or formed on the passivation layer PSV.The bank patterns BNP may be located on the bottom of alignmentelectrodes ALE to overlap with a portion of each of the alignmentelectrodes ALE.

In one or more embodiments, the bank patterns BNP may be formed asseparated patterns individually located corresponding to each pixel PXL.For example, in each pixel area PXA, bank patterns BNP corresponding tosub-pixels SPX of a corresponding pixel PXL may be integrally formed tobe substantially formed as one bank pattern BNP. A bank pattern BNPcorresponding to each pixel PXL may be considered as a componentincluded in the corresponding pixel PXL (or light-emitting units EMUprovided in the pixel PXL), or may be considered as a component to beprovided in the pixel PXL separately from the pixel PXL.

In one or more other embodiments, bank patterns BNP corresponding to atleast two adjacent pixels PXL may be integrally formed, to besubstantially formed as one bank pattern BNP. For example, bank patternsBNP corresponding to pixels PXL that are located on each horizontal lineand that are arranged in the first direction DR1 may be integrallyformed. A portion of a bank pattern BNP corresponding to each pixel PXLmay be considered as a component included in the corresponding pixel PXL(or light-emitting units EMU provided in the pixel PXL), or may beconsidered as a component to be provided in the pixel PXL separatelyfrom the pixel PXL.

Each bank pattern BNP may include openings OPN corresponding tolight-emitting element arrangement areas AR of sub-pixels SPX providedin a corresponding pixel(s) PXL. For example, the bank pattern BNP mayinclude first openings OPN1 corresponding to first light-emittingelement arrangement areas AR1 in which first light-emitting elements LDLof first, second, and third sub-pixels SPX1, SPX2, and SPX3 provided inthe corresponding pixel(s) PXL are located, and/or second openings OPN2corresponding to second light-emitting element arrangement areas AR2 inwhen second light-emitting elements LD2 of the first, second, and thirdsub-pixels SPX1, SPX2, and SPX3 are located.

By the bank patterns BNP, alignment electrodes ALE may protrude in anupper direction (e.g., the third direction DR3) at the periphery oflight-emitting elements LD. The bank patterns BNP and the alignmentelectrodes ALE may form reflective protrusion patterns at the peripheryof the light-emitting elements LD. Accordingly, the light efficiency ofthe sub-pixels SPX can be improved.

The bank patterns BNP may include an inorganic insulating materialand/or an organic insulating material, and may have a single-layerstructure or a multilayer structure. In one or more embodiments, thebank patterns BNP may be an organic layer pattern including an organicinsulating material, and upper surfaces of the bank patterns BNP may besubstantially flat. However, when the surface of the circuit layer PCLhas a bending (e.g., an uneven shape), the bank patterns BNP may have aslight bending corresponding to the bending of the circuit layer PCL.For example, the bank patterns BNP may be formed to be relatively highat a portion at which the surface of the circuit layer PCL has a maximumheight.

Alignment electrodes ALE of light-emitting units EMU may be located overthe bank patterns BNP.

The alignment electrodes ALE may include a conductive material, and thematerial constituting the alignment electrodes ALE is not particularlylimited. In one or more embodiments, the alignment electrodes ALE mayinclude at least one metal or any alloy including the same among variousmetallic materials including silver (Ag), magnesium (Mg), aluminum (Al),platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd),iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper(Cu), and the like, a conductive oxide such as Indium Tin Oxide (ITO),Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), Zinc Oxide (ZnO),Aluminum doped Zinc Oxide (AZO), Gallium doped Zinc Oxide (GZO), ZincTin Oxide (ZTO), Gallium Tin Oxide (GTO), and Fluorine doped Tin Oxide(FTO), at least one conductive material among conductive polymers suchas PEDOT, carbon nano tubes, graphene, and/or another conductivematerial.

The first alignment electrode ALE1 and the second alignment electrodeALE2 may be adjacent to each other, and may be spaced apart from eachother. For example, the first alignment electrode ALE1 and the secondalignment electrode ALE2 may be adjacent to each other in the firstdirection DR1, and may be spaced apart from each other in the firstdirection DR1. At least one first light-emitting element LD1 may belocated between the first alignment electrode ALE1 and the secondalignment electrode ALE2 (or in a first light-emitting elementarrangement area AR1 corresponding thereto).

The second alignment electrode ALE2 and the third alignment electrodeALE3 may be adjacent to each other, and may be spaced apart from eachother. For example, the second alignment electrode ALE2 and the thirdalignment electrode ALE3 may be adjacent to each other in the firstdirection DR1, and may be spaced apart from each other in the firstdirection DR1. In one or more embodiments, in an emission area EA ofeach sub-pixel SPX, the first alignment electrode ALE1, the secondalignment electrode ALE2, and the third alignment electrode ALE3 may besequentially located along the first direction DR1. At least one secondlight-emitting element LD2 may be located between the second alignmentelectrode ALE2 and the third alignment electrode ALE3 (or in a secondlight-emitting element arrangement area AR2 corresponding thereto). Thenumber, shapes, sizes, and/or positions of alignment electrodes ALElocated in each emission area EA may be changed in some embodiments.

Each of the alignment electrodes ALE may be a single layer or amultilayer. In one or more embodiments, each alignment electrode ALE mayinclude a reflective electrode layer including a reflective conductivematerial (e.g., a metal), and a single-layer electrode or a multilayerelectrode.

The first insulating layer INS1 may be located on the alignmentelectrodes ALE. In one or more embodiments, the first insulating layerINS1 may include contact holes (e.g., fourth and fifth contact holes CH4and CH5 shown in FIG. 9 ) for electrically connecting at least somealignment electrodes ALE (e.g., the first and second alignmentelectrodes ALE1 and ALE2) respectively to contact electrodes CNE (e.g.,first and third contact electrodes CNE1 and CNE3) corresponding thereto.

The first insulating layer INS1 may be a single layer or a multilayer,and may include an inorganic insulating material and/or an organicinsulating material. In one or more embodiments, the first insulatinglayer INS1 may include silicon nitride (SiN_(x)), silicon oxide(SiO_(x)), silicon oxynitride (SiO_(x)N_(y)), or another insulatingmaterial.

As the alignment electrodes ALE are covered by the first insulatinglayer INS1, the likelihood of the alignment electrodes ALE being damagedin a subsequent process can be reduced or prevented. In addition, thelikelihood of a short-circuit defect as alignment electrodes ALE andlight-emitting elements LD are inappropriately connected to each othercan be reduced or prevented.

The first bank BNK1 may be located in the display area DA in which thealignment electrodes ALE and the first insulating layer INS1 are formed.The first bank BNK1 may have openings corresponding to emission areas EAof sub-pixels SPX, and may be formed in a non-emission area NEA tosurround the emission areas EA of the sub-pixels SPX. Each emission areaEA to which light-emitting elements LD are to be supplied may be defined(or partitioned) by the first bank BNK1.

In one or more embodiments, the first bank BNK1 may include a blackmatrix material, or another light-blocking material and/or a reflectivematerial in addition to the black matrix material. The first bank BNK1may include an inorganic insulating material and/or an organicinsulating material, and may have a single-layer structure or amultilayer structure. In one or more embodiments, the first bank BNK1may be an organic layer pattern including an organic insulatingmaterial, and may have a relatively gentle bending (e.g., a slightunevenness). In one or more embodiments, the first bank BNK1 may havepartially different heights respectively due to patterns locatedthereunder. In one or more embodiments, a portion of the first bankBNK1, which overlaps with the bank patterns BNP, may be relativelyhigher than the other portion of the first bank BNK1.

Light emitting elements LD may be supplied to each emission area EAsurrounded by the first bank BNK1. The light-emitting elements LD may belocated and/or aligned between a pair of alignment electrodes ALE byalignment signals respectively applied to alignment electrodes ALE(e.g., a first alignment line, a second alignment line, and/or a thirdalignment line before the alignment electrodes ALE are separated into afirst alignment electrode ALE1, a second alignment electrode ALE2,and/or a third alignment electrode ALE3 of each pixel PXL or eachsub-pixel SPX). For example, the light-emitting elements LD supplied toeach emission area EA may be respectively located and/or aligned betweenthe first alignment electrode ALE1 and the second alignment electrodeALE2, and between the second alignment electrode ALE2 and the thirdalignment electrode ALE3.

In one or more embodiments, a first light-emitting element(s) LD1located and/or aligned in a first light-emitting element arrangementarea AR1 between the first alignment electrode ALE1 and the secondalignment electrode ALE2 may be arranged in the first direction DR1, anoblique direction, or the like such that a first end portion(s) of thefirst light-emitting element(s) LD1 is/are adjacent to the firstalignment electrode ALE1 and such that a second end portion(s) of thefirst light-emitting element(s) LD1 is/are adjacent to the secondalignment electrode ALE2.

A second light-emitting element(s) LD2 located and/or aligned in asecond light-emitting element arrangement area AR2 between the secondalignment electrode ALE2 and the third alignment electrode ALE3 may bearranged in the first direction DR1, an oblique direction, or the likesuch that a first end portion(s) of the second light-emitting element(s)LD2 is/are adjacent to the third alignment electrode ALE3, and such thata second end portion(s) of the second light-emitting element(s) LD2is/are adjacent to the second alignment electrode ALE2. The arrangementpositions and/or direction of light-emitting elements LD may be changedin some embodiments.

The second insulating layer INS2 may be located on a portion of each ofthe light-emitting elements LD. In one or more embodiments, the secondinsulating layer INS2 is entirely formed in the display area DA, and mayinclude openings opened at first and second end portions EP1 and EP2 oflight-emitting elements LD aligned in an emission area EA of acorresponding sub-pixel SPX and the periphery thereof (e.g., an areacorresponding to alignment electrodes ALE and/or contact electrodesCNE). In one or more other embodiments, the second insulating layer INS2may include separated insulating patterns locally located only on aportion including central portions of light-emitting elements LD alignedin each emission area EA (or each light-emitting element arrangementarea AR provided in the emission area EA) to expose first and second endportions EP1 and EP2 of the light-emitting element LD. When the secondinsulating layer INS2 is formed on the top of light-emitting elementsLD, the light-emitting elements LD can be stably fixed.

The second insulating layer INS2 may be a single layer or a multilayer,and may include an inorganic insulating material and/or an organicinsulating material. For example, the second insulating layers INS2 mayinclude silicon nitride (SiN_(x)), silicon oxide (SiO_(x)), siliconoxynitride (SiO_(x)N_(y)), aluminum oxide (Al_(x)O_(y)), a photoresistmaterial, or another insulating material.

Different contact electrodes CNE may be located and/or formed on firstand second end portions EP1 and EP2 of light-emitting elements LD thatare not covered by the second insulating layer INS2. For example, thefirst contact electrode CNE1 may be located on a first end portion EP1of the first light-emitting element LD1, and a portion of the secondcontact electrode CNE2 (e.g., a left pattern portion of the secondcontact electrode CNE2) may be located on a second end portion EP2 ofthe first light-emitting element LD1. Another portion of the secondcontact electrode CNE2 (e.g., a right pattern portion of the secondcontact electrode CNE2) may be located on a first end portion EP1 of thesecond light-emitting element LD2, and the third contact electrode CNE3may be located on a second end portion EP2 of the second light-emittingelement LD2.

Although a case where the second contact electrode CNE2 located on thesecond end portion EP2 of the first light-emitting element LD1, and thesecond contact electrode CNE2 located on the first end portion EP1 ofthe second light-emitting element LD2, are separated from each other isillustrated in FIG. 7 , the second contact electrode CNE2 located on thesecond end portion EP2 of the first light-emitting element LD1, and thesecond contact electrode CNE2 located on the first end portion EP1 ofthe second light-emitting element LD2, may be integrally ornon-integrally connected to each other to thereby constitute one secondcontact electrode CNE2. For example, when viewed on a plane, the secondcontact electrode CNE2 located on the second end portion EP2 of thefirst light-emitting element LD1, and the second contact electrode CNE2located on the first end portion EP1 of the second light-emittingelement LD2, may be integrally connected to each other. The secondcontact electrode CNE2 may be electrically connected to the firstcontact electrode CNE1 via the first light-emitting element LD1, and maybe electrically connected to the third contact electrode CNE3 via thesecond light-emitting element LD2.

In one or more embodiments, the first contact electrode CNE1 may bedirectly formed on the first end portion EP1 of the first light-emittingelement LD1, to be electrically connected to the first end portion EP1of the first light-emitting element LD1. The second contact electrodeCNE2 may be directly formed on the second end portion EP2 of the firstlight-emitting element LD1 and on the first end portion EP1 of thesecond light-emitting element LD2 to be electrically connected to thesecond end portion EP2 of the first light-emitting element LD1 and tothe first end portion EP1 of the second light-emitting element LD2. Thethird contact electrode CNE3 may be directly formed on the second endportion EP2 of the second light-emitting element LD2 to be electricallyconnected to the second end portion EP2 of the second light-emittingelement LD2. Meanwhile, when each sub-pixel SPX includes only a singlelight-emitting element LD as illustrated in the one or more embodimentscorresponding to FIG. 4 , or when each sub-pixel SPX includes alight-emitting unit EMU having a parallel structure, the sub-pixel SPXmay include only a pair of contact electrodes CNE respectively locatedon first end portions EP1 and on second end portions EP2 oflight-emitting elements LD.

The first contact electrode CNE1 may be located on the top of the firstalignment electrode ALE1 to overlap with the first alignment electrodeALE1. The second contact electrode CNE2 may be located on the top of thesecond alignment electrode ALE2 and the third alignment electrode ALE3to overlap with a portion of the second alignment electrode ALE2 and thethird alignment electrode ALE3. The third contact electrode CNE3 may beon the top of the second alignment electrode ALE2 to overlap withanother portion of the second alignment electrode ALE2.

In one or more embodiments, the first alignment electrode ALE1 and thefirst contact electrode CNE1 may be electrically connected to each otherthrough at least one contact hole (e.g., a fourth contact hole CH4 shownin FIG. 9 ). Similarly, the second alignment electrodes ALE2 and thethird contact electrode CNE3 may be electrically connected to each otherthrough at least another contact hole (e.g., a fifth contact hole CH5shown in FIG. 9 ). A first alignment electrode ALE1 and/or a firstcontact electrode CNE1 of each sub-pixel SPX may be electricallyconnected to a pixel circuit PXC of the corresponding sub-pixel SPXthrough at least one contact hole (e.g., a first contact hole CH1 shownin FIGS. 8 and 9 ). Second alignment electrodes ALE2 and/or a thirdcontact electrode CNE3 of each sub-pixel SPX may be electricallyconnected to the second power line PL2 through at least another contacthole (e.g., a second contact hole CH2 shown in FIGS. 8 and 9 ).

The contact electrodes CNE may include a conductive material. In one ormore embodiments, the contact electrodes CNE may include a transparentconductive material to allow light generated from light-emittingelements LD to be transmitted therethrough. For example, the contactelectrodes CNE may include at least one conductive material among indiumtin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO),zinc oxide (ZnO) or indium oxide (In₂O₃), or another transparentconductive material.

The first contact electrode CNE1, the second contact electrode CNE2,and/or the third contact electrode CNE3 may be formed in the same layeror in different layers. For example, the mutual positions and/orformation order of the first contact electrode CNE1, the second contactelectrode CNE2, and the third contact electrode CNE3 may be variouschanged in some embodiments.

In one or more embodiments, the first contact CNE1 and the third contactelectrode CNE3 may be first formed on the second insulating layer INS2.The first contact CNE1 and the third contact electrode CNE3 may beconcurrently/substantially simultaneously or sequentially formed.Subsequently, the third insulating layer INS3 may be formed to cover thefirst contact CNE1 and the third contact electrode CNE3, and the secondcontact electrode CNE2 may be formed in each emission area EA in whichthe third insulating layer INS3 is formed.

In one or more other embodiments, the second contact electrode CNE2 maybe first formed on the second insulating layer INS2. Subsequently, thethird insulating layer INS3 may be formed in each emission area EA tocover at least the second contact electrode CNE2, and the first contactelectrode CNE1 and the third contact electrode CNE3 may be formed eachemission area EA in which the third insulating layer INS3 is formed. Thefirst contact electrode CNE1 and the third contact electrode CNE3 may beconcurrently/substantially simultaneously or sequentially formed.

In one or more embodiments, the third insulating layer INS3 is entirelyformed in the display area DA, and may include/define openings opened inan area corresponding to second contact electrodes CNE2 of sub-pixelsSPX (or first and third contact electrodes CNE1 and CNE3 of thesub-pixels SPX). In one or more other embodiments, the third insulatinglayer INS3 may include separated insulating patterns individually formedfor each emission area EA to cover first and third contact electrodesCNE1 and CNE3 (or a second contact electrode CNE2) formed in eachemission area EA.

The third insulating layer INS3 may be a single layer or a multilayer,and may include an inorganic insulating material and/or an organicinsulating material. For example, the third insulating layer INS3 mayinclude silicon nitride (SiN_(x)), silicon oxide (SiO_(x)), siliconoxynitride (SiO_(x)N_(y)), aluminum oxide (Al_(x)O_(y)), a photoresistmaterial, or another insulating material. The first insulating layerINS1, the second insulating layer INS2, and/or the third insulatinglayer INS3 may include the same insulating material or include differentinsulating materials.

When contact electrodes CNE (e.g., first and second contact electrodesCNE1 and CNE2, or second and third contact electrodes CNE2 and CNE3)located on first and second end portions EP1 and EP2 of respectivelight-emitting elements LD are located in different layers by using thethird insulating layer INS3, the contact electrodes CNE can be stablyseparated from each other, and the likelihood of a short-circuit defectcan be prevented or reduced.

In some embodiments, the first contact electrode CNE1, the secondcontact electrode CNE2, and the third contact electrode CNE3 may belocated in the same layer of the display layer DPL, and may beconcurrently/substantially simultaneously or sequentially formed. Thedisplay area DA may not include the third insulating layer INS3. Whenthe contact electrodes CNE are concurrently/substantially simultaneouslyformed in the same layer, a pixel process can be simplified, andmanufacturing efficiency can be improved.

In one or more embodiments, the display device DD may further includethe light conversion layer CCL and the second bank BNK2, which areprovided above the light-emitting elements LD. The color conversionlayer CCL may be located in each emission area EA in which thelight-emitting elements LD are located. The second bank BNK2 may belocated in the non-emission area NEA to overlap with the first bankBNK1.

The second bank BNK2 may define (or partition) each emission area EA inwhich the light conversion layer CCL is to be formed. In one or moreembodiments, the second bank BNK2 may be integrated with the first bankBNK1.

The second bank BNK2 may include a black matrix material, or anotherlight-blocking material, and/or a reflective material in addition to theblack matrix material. The second bank BNK2 may include the samematerial as the first bank BNK1, or may include a material differentfrom the material of the first bank BNK1.

The light conversion layer CCL may include light conversion particlesLCP corresponding to each sub-pixel SPX. The light conversion particlesLCP may include wavelength conversion particles (or color conversionparticles) for converting a wavelength and/or a color of light emittedfrom light-emitting elements LD located in a corresponding emission areaEA, and/or light-scattering particles for improving light emissionefficiency by scattering light emitted from the light-emitting elementsLD. In one or more embodiments, each light conversion layer CCLincluding wavelength conversion particles including at least one kind ofquantum dot (e.g., a red quantum dot, a green quantum dot, and/or a bluequantum dot) and/or light-scattering particles SCT may be provided on alight-emitting unit EMU of each sub-pixel SPX.

For example, when a sub-pixel SPX is set as a red (or green) sub-pixel,and blue light-emitting elements LD are provided to a light-emittingunit EMU of the sub-pixel SPX, a color conversion layer CCL including ared (or green) quantum dot for converting blue light into red (or green)light may be located on the light-emitting unit EMU of the sub-pixelSPX. In one or more embodiments, the light conversion layer CCL mayfurther include light-scattering particles. When a sub-pixel SPX is setas a blue sub-pixel, and blue light-emitting elements LD are provided toa light-emitting unit EMU of the sub-pixel SPX, a color conversion layerCCL including light-scattering particles may be provided on thelight-emitting unit EMU of the sub-pixel SPX, or the light conversionlayer CCL may be omitted.

The fourth insulating layer INS4 may be formed on the one surface of thebase layer BSL including light-emitting units EMU and/or lightconversion layers CCL of the sub-pixels SPX.

The fourth insulating layer INS4 may be a single layer or a multilayer,and may include an organic insulating material and/or an inorganicinsulating material. The fourth insulating layer INS4 may protect thelight-emitting units EMU and/or the light conversion layers CCL. In oneor more embodiments, the fourth insulating layer INS4 may include anorganic layer including an organic insulating material, and mayplanarize a surface of the display layer DPL.

The color filter layer CFL may be located on the fourth insulating layerINS4. The color filter layer CFL may include color filters CFcorresponding to a color of sub-pixels SPX. For example, the colorfilter layer CFL may include a first color filter CF1 located in theemission area EA of the first sub-pixel SPX1, a second color filter CF2located in the emission area EA of the second sub-pixel SPX2, and athird color filter CF3 located in the emission area EA of the thirdsub-pixel SPX3. Each color filter CF may be provided on a light-emittingunit EMU of a corresponding sub-pixel SPX to overlap with thelight-emitting unit EMU.

In one or more embodiments, the first, second, and third color filtersCF1, CF2, and CF3 may overlap with each other in the non-emission areaNEA, and accordingly, light can be blocked from being transmittedthrough the non-emission area NEA. In one or more other embodiments, thefirst, second, and third color filters CF1, CF2, and CF3 may be formedin emission areas EA of the sub-pixels SPX to be separated from eachother, and a separate light blocking pattern or the like may be locatedbetween the first, second, and third color filters CF1, CF2, and CF3.

The encapsulation layer ENC may be located on the color filter layerCFL. The encapsulation layer ENC may include a fifth insulating layerINS5. The fifth insulating layer INS5 may be a single layer or amultilayer, and may include an organic insulating material and/or aninorganic insulating material. In one or more embodiments, the fifthinsulating layer INS5 may be entirely formed in at least the displayarea DA to cover the circuit layer PCL, the display layer DPL, and/orthe color filter layer CFL, and planarize a surface of the display panelDPN. In one or more other embodiments, the display panel DPN may bemanufactured not to include the encapsulation layer ENC, and aprotective film and the like, which are separately manufactured, may beattached onto the display panel DPN.

FIG. 8 is a plan view illustrating a circuit layer PCL of the displayarea DA in accordance with one or more embodiments of the presentdisclosure. For example, FIG. 8 illustrates one or more embodiments of astructure of the circuit layer PCL, based on an area in which pixelcircuits PXC of the first pixel PXL1 and the second pixel PXL2 (shown inFIG. 6 ), and in which lines at the periphery thereof, are located.

In one or more embodiments, the pixels PXL including the first pixelPXL1 and the second pixel PXL2, which are located in the display areaDA, may have structures that are substantially similar or identical toone another. Accordingly, in FIG. 8 , a structure of pixel circuits PXCprovided in each pixel PXL will be described based on circuit elementsconstituting first, second, and third pixel circuits PXC1, PXC2, andPXC3 of the first pixel PXL1.

Referring to FIGS. 3 to 8 , the circuit layer PCL may include pixelcircuits PXC of sub-pixels SPX located in each pixel area PXA. Forexample, the circuit layer PCL may include a first pixel circuit PXC1, asecond pixel circuit PXC2, and a third pixel circuit PXC3 respectivelylocated a first circuit area SPXA1, a second circuit area SPXA2, and athird circuit area SPXA3 of a corresponding pixel area PXA.

The circuit layer PCL may further include lines electrically connectedto the pixels PXL. For example, the circuit layer PXL may include scanlines SL, data lines DL, sensing lines SENL, a first power line PL1(e.g., a mesh-shaped first power line PL1 including first horizontalpower lines HPL1 and first vertical power lines VPL1), and a secondpower line PL2 (e.g., a mesh-shaped second power line PL2 includingsecond horizontal power lines HPL2 and second vertical power linesVPL2). In one or more embodiments, the circuit layer PCL may furtherinclude connection lines CL electrically connected to the scan lines SL.The arrangement structure, extending direction, and/or positions on asection of the scan lines SL, the data lines DL, the sensing lines SENL,the first power line PL1, the second power line PL2, and the connectionlines CL have been in the embodiments shown in FIGS. 6 and 7 , andtherefore, overlapping descriptions will be omitted.

The circuit layer PCL may further include contact holes CH forelectrically connecting circuit elements, electrodes, conductivepatterns, and/or lines, which are located in the circuit layer PCL, toeach other. In FIG. 8 , a reference numeral may be given to only onecontact hole CH (e.g., a contact hole CH for electrically connecting annth scan line and gate electrodes GE of second and third transistors M2and M3 to each other) representing contact holes CH for connectingcorresponding components in the circuit layer PCL.

In one or more embodiments, at least one line may be formed as amultilayer line at at least one portion. For example, the connectionlines CL including an nth connection line CLn and an (n+1)th connectionline CLn+1 may be formed as multilayer lines including a main line ML1located in the same layer as bottom metal layers BML, a first sub-lineSLI1 located in the same layer gate electrodes GE, and a second sub-lineSLI2 located in the same layer as source and drain electrodes SE and DE.Accordingly, a delay of a power voltage (e.g., a first power voltage VDDand/or a second power voltage VSS) or a signal (e.g., scan signals),which is supplied to the multilayer lines, can be prevented or reduced,and the pixels PXL can be stably driven.

The circuit layer PCL may further include/define first contact holesCH1, second contact holes CH2, and third contact holes CH3, which areformed between the circuit layer PCL and the display layer DPL.

Each first contact hole CH1 may allow the electrical connection of eachpixel circuit PXC, and a light-emitting unit EMU corresponding thereto,to each other. For example, a first contact hole CH1 corresponding toeach first sub-pixel SPX1 may be formed between the first pixel circuitPXC1 and a first alignment electrode ALE1 of a first light-emitting unitEMU1, and may allow the first pixel circuit PXC1 and the firstlight-emitting unit EMU1 to be electrically connected to each other. Afirst contact hole corresponding to each second sub-pixel SPX2 may beformed between the second pixel circuit PXC2 and a first alignmentelectrode ALE1 of a second light-emitting unit EMU2, to therebyelectrically connect the second pixel circuit PXC2 and the secondlight-emitting unit EMU2 to each other. A first contact hole CH1corresponding to each third sub-pixel SPX3 may be formed between thethird pixel circuit PXC3 and a first alignment electrode ALE1 of a thirdlight-emitting unit EMU3 to thereby electrically connect the third pixelcircuit PXC3 and the third light-emitting unit EMU3.

The second contact holes CH2 may electrically connect the second powerline PL2 and second alignment electrodes ALE2 of light-emitting unitsEMU. For example, the second contact holes CH2 may be formed betweensecond horizontal power lines HPL2 repeatedly located for every two ormore horizontal lines and second alignment electrodes ALE2 oflight-emitting units EMU located at the periphery of the secondhorizontal power lines HPL2 (e.g., overlapping with the secondhorizontal power lines HPL2). Accordingly, in a manufacturing process ofpixels PXL (e.g., an alignment process of light-emitting elements LD), asecond alignment signal may be supplied to the second alignmentelectrodes ALE2 through the second power line PL2.

The third contact holes CH3 may electrically connect/allow theelectrical connection of the first power line PL1 and floating patterns(e.g. floating patterns FPT shown in FIG. 9 ) of the display layer DPLto each other. For example, the third contact holes CH3 may be formedbetween first horizontal power lines HPL1 repeatedly located for everytwo or more horizontal lines and floating patterns FPT overlapping withthe first horizontal power lines HPL1. In one or more embodiments, thefloating patterns FPT may be integrally formed respectively with firstalignment electrodes ALE1 and third alignment electrodes ALE3 in a pixelprocess (e.g., a process for forming pixels PXL on the base layer BSL).Therefore, the floating patterns FPT along with the first alignmentelectrodes ALE1 and the third alignment electrodes ALE3 constitute afirst alignment line. Accordingly, in an alignment process of thelight-emitting elements LD, a first alignment signal may be supplied tothe first alignment line through the first power line PL1. After thealignment process of the light-emitting elements LD is completed, thefirst alignment line is cut off at the periphery of the third contactholes CH3, so that the floating patterns FPT are separated from thefirst alignment electrodes ALE1. Accordingly, the sub-pixels SPX can beindividually driven. In some embodiments, the floating patterns FPT maybe separated from the third alignment electrodes ALE3.

Each of the first contact holes CH1, the second contact holes CH2, andthe third contact holes CH3 may be configured as a single contact hole(or contact part) or a via hole, which is formed at a correspondingposition, or may include two or more contact holes and/or two or morevia holes, which are densely formed at a corresponding position, and mayconnect the same components to each other.

Each pixel circuit PXC may include a first transistor M1, a secondtransistor M2, a third transistor M3, and a capacitor Cst, which arelocated in each circuit area SPXA. For example, the first pixel circuitPXC1 may include a first transistor M1, a second transistor M2, a thirdtransistor M3, and a capacitor Cst, which are located a first circuitarea SPXA1 of a corresponding pixel area PXA. The second pixel circuitPXC2 may include a first transistor M1, a second transistor M2, a thirdtransistor M3, and a capacitor Cst, which are located a second circuitarea SPXA2 of a corresponding pixel area PXA. The third pixel circuitPXC3 may include a first transistor M1, a second transistor M2, a thirdtransistor M3, and a capacitor Cst, which are located a third circuitarea SPXA3 of a corresponding pixel area PXA.

Each first transistor M1 may include a first semiconductor pattern SCP1,a first gate electrode GE1, a first source electrode SE1, and a firstdrain electrode DE1. In one or more embodiments, each first transistorM1 may further include a bottom metal layer BML.

The bottom metal layer BML may overlap with the first semiconductorpattern SCP1, the first gate electrode GE1, and the first sourceelectrode SE1. In one or more embodiments, the bottom metal layer BMLmay be electrically connected to the first source electrode SE1 throughat least one contact hole CH.

The first semiconductor pattern SCP1 may overlap with the first gateelectrode GE1 and the bottom metal layer BML, and may be connected tothe first source electrode SE1 and the first drain electrode DE1. Forexample, respective end portions of the first semiconductor pattern SCP1may be electrically connected to the first source electrode SE1 and thefirst drain electrode DE1 through contact holes CH, respectively.

The first gate electrode GE1 may be connected to a lower electrode LE ofthe capacitor Cst and to a second source electrode SE2. For example, thefirst gate electrode GE may be integrally formed with the lowerelectrode LE of the capacitor CST, and may be electrically connected tothe second source electrode SE2 through at least one contact hole CH.

The first source electrode SE1 may be connected to an upper electrode UEof the capacitor Cst and to a third source electrode SE3. For example,the first source electrode SE1 may be integrally formed with the upperelectrode UE of the capacitor Cst and the third source electrode SE3.The first source electrode SE1 may be connected to a light-emitting unitEMU of a corresponding sub-pixel SPX. For example, the first sourceelectrode SE1 may be electrically connected to a first alignmentelectrode ALE1 and/or to a first contact electrode CNE1, and may beformed in the light-emitting unit EMU of the corresponding sub-pixelSPX. In one or more embodiments, the first source electrode SE1 of thefirst pixel circuit PXC1, the upper electrode UE of the capacitor Cst,and the third source electrode SE3 may be electrically connected to thefirst alignment electrode ALE1 of the first light-emitting unit EMU1through the first contact hole CH1 formed between the first pixelcircuit PXC1 and the first light-emitting unit EMU1, and may beelectrically connected to a first contact electrode CNE1 of the firstlight-emitting unit EMU1.

The first drain electrode DE1 may be connected to the first power linePL1. For example, the first drain electrode DE1 may be electricallyconnected to a first vertical power line VPL1 through at least onecontact hole CH.

Each transistor M2 may include a second semiconductor pattern SCP2, asecond gate electrode GE2, the second source electrode SE2, and a seconddrain electrode DE2.

The second semiconductor pattern SCP2 may overlap with the second gateelectrode GE2, and may be connected to the second source electrode SE2and the second drain electrode DE2. For example, respective end portionsof the second semiconductor pattern SCP2 may be electrically connectedto the second source electrode SE2 and the second drain electrode DE2through contact holes CH, respectively.

The second gate electrode GE2 may be connected to a scan line SL. Forexample, the second gate electrode GE2 may be electrically connected toa scan line SL (e.g., an nth scan line SLn) of a correspondinghorizontal line through at least one contact hole CH.

The second source electrode SE2 may be connected to the lower electrodeLE of the capacitor Cst and the first gate electrode GE1. For example,the second source electrode SE2 may be electrically connected to thelower electrode LE of the capacitor Cst and the first gate electrode GE1through at least one contact hole CH.

The second drain electrode DE2 may be connected to a sub-data line of acorresponding sub-pixel SPX. For example, a second drain electrode DE2of the first pixel circuit PXC1 may be electrically connected to a firstsub-data line D1 through at least one contact hole CH. A second drainelectrode DE2 of the second pixel circuit PXC2 may be electricallyconnected to a second sub-data line D2 through at least one contact holeCH. A second drain electrode DE2 of the third pixel circuit PXC3 may beelectrically connected to a third sub-data line D3 through at least onecontact hole CH.

Each third transistor M3 may include a third semiconductor pattern SCP3,a third gate electrode GE3, the third source electrode SE3, and a thirddrain electrode DE3.

The third semiconductor pattern SCP3 may overlap with the third gateelectrode GE3, and may be connected to the third source electrode SE3and the third drain electrode DE3. For example, respective end portionsof the third semiconductor pattern SCP3 may be electrically connected tothe third source electrode SE3 and the third drain electrode DE3 throughcontact holes CH.

The third gate electrode GE may be connected to each scan line SL, ormay be connected to a separate control line SSL separated from the scanline SL. In one or more embodiments, the third gate electrode GE3 may beintegrally formed with the second gate electrode GE2, and may beelectrically connected to each scan line SL through at least one contacthole CH.

The third source electrode SE3 may be connected to the upper electrodeUE of the capacitor Cst and the first source electrode SE1. For example,the third source electrode SE3 may be integrally formed with the upperelectrode UE of the capacitor Cst and the first source electrode SE1.

The third drain electrode DE3 may be connected to a sensing line SENL.For example, the third drain electrode DE3 may be electrically connectedto the corresponding sensing line SENL through at least one contact holeCH.

The capacitor Cst may include the lower electrode LE and the upperelectrode UE.

The lower electrode LE of the capacitor Cst may be connected to thefirst gate electrode GE1 and the second source electrode SE2. Forexample, the lower electrode LE of the capacitor Cst may be integrallyformed with the first gate electrode GE1, and may be electricallyconnected to the second source electrode SE2 through at least onecontact hole CH.

The upper electrode UE of the capacitor Cst may be connected to thefirst source electrode SE1 and the third source electrode SE3. Forexample, the upper electrode UE of the capacitor Cst may be integrallyformed with the first source electrode SE1 and the third sourceelectrode SE3.

In one or more embodiments, the bottom metal layers BML and at leastsome lines (or portions of the lines) extending in the second directionDR2, which are provided in the display area DA, may be located in thesame layer of the circuit layer PCL (e.g., the first conductive layerinside the circuit layer PCL). The semiconductor patterns SCP providedin the display area DA may be located in the same layer of the circuitlayer PCL (e.g., the semiconductor layer inside the circuit layer PCL).The gate electrodes GE, the lower electrodes LE of the capacitors Cst,and/or at least one sub-line (e.g., the first sub-lines SLI1 of theconnection lines CL), which are provided in the display area DA, may belocated in the same layer of the circuit layer PCL (e.g., the secondconductive layer (e.g., a gate layer) inside the circuit layer PCL). Thesource electrodes SE, the drain electrodes DE, the upper electrodes UEof the capacitors Cst, at least some lines extending in the firstdirection DR1, and/or at least one sub-line (e.g., the second sub-linesSLI2 of the connection lines CL), which are provided in the display areaDA, may be located in the same layer of the circuit layer PCL (e.g., thethird conductive layer (e.g., a source-drain layer) inside the circuitlayer PCL).

In the one or more embodiments corresponding to FIGS. 6 to 8 , thecircuit elements and the lines of the circuit layer PCL are efficientlylocated, so that the area occupied by each pixel circuit PXC can bereduced or minimized. Accordingly, the above-described embodiments canbe usefully applied to a high-resolution display device DD in which thearea of a pixel area PXA is narrow, and the like

In addition, in the second direction DR2, lines extending in the firstdirection DR1 may be located at respective sides of light-emitting unitsEMU of sub-pixels SPX to be immediately adjacent to the light-emittingunits EMU. For example, in the second direction DR2, the nth scan lineSLn and the first horizontal power line HPL1 may be located atrespective sides of light-emitting units EMU provided in the first pixelPXL1 to be immediately adjacent to the light-emitting units EMU of thefirst pixel PXL1. Similarly, the (n+1)th scan line SLn+1 and the secondhorizontal power line HPL2 may be located at respective sides oflight-emitting units EMU provided in the second pixel PXL2 to beimmediately adjacent to the light-emitting units EMU of the second pixelPXL2. Accordingly, in the display layer DPL formed on the circuit layerPCL, the height of a bank (e.g., a first bank BNK1 shown in FIG. 9 ) canbe increased or maximized.

Thus, the capacity of emission areas EA can be increased, and overflowof a light-emitting element ink including light-emitting elements LDover the non-emission area NEA adjacent to both ends of the emissionareas EA (e.g., the non-emission area NEA that is adjacent to theemission areas EA in the second direction DR2, and that has end portionsof first alignment electrodes ALE1, which are located therein) in aprocess of supplying the light-emitting elements LD to the emissionareas EA, can be prevented or reduced. Accordingly, a first alignmentline can be stably separated into first alignment electrodes ALE1(and/or third alignment electrodes ALE3) in a subsequent process. Inaccordance with the above-described embodiments, a short-circuit defectoccurring in the display area DA (e.g., a short-circuit defect that mayoccur because first alignment electrodes ALE1 are not stably separated)can be prevented and reduced.

FIG. 9 is a plan view illustrating a display layer DPL of the displayarea DA in accordance with one or more embodiments of the presentdisclosure. For example, FIG. 9 illustrates one or more embodiments of astructure of the display layer DPL, based on an area in whichlight-emitting units EMU of the first pixel PXL1 and the second pixelPXL2, which are shown in FIG. 6 , and in which a bank pattern BNP and afirst bank BNK1 at the periphery thereof, are located. In FIG. 9 , somelines located in the circuit layer PCL (e.g., an nth scan line SLn, an(n+1)th scan line SLn+1, a first horizontal power line HPL1, and asecond horizontal power line HPL2, which are located inside and/or theperiphery of the first pixel PXL1 and the second pixel PXL2) areindicated by a dotted line such that positions of the light-emittingunits EMU in accordance with the above embodiments can be more clearlyrepresented.

FIGS. 10 and 11 are plan views illustrating display layers DPL of thedisplay area DA in accordance with embodiments of the presentdisclosure. For example, FIGS. 10 and 11 illustrate differentembodiments in relation to bank patterns BNP, based on an area in whichfour pixels PXL (e.g., a first pixel PXL1, a second pixel PXL2, a thirdpixel PXL3, and a fourth pixel PXL4) adjacent to each other in the firstdirection DR1 and the second direction DR2 are located.

FIG. 12 is a sectional view illustrating a display area DA in accordancewith one or more embodiments of the present disclosure. For example,FIG. 12 schematically illustrates a section of the display area DA,which corresponds to the line II-II′ shown in FIG. 9 .

First, referring to FIGS. 3 to 9 , sub-pixels SPX of each pixel PXL mayinclude emission areas EA arranged in the first direction DR1, andlight-emitting units EMU provided in the emission areas EA.

In one or more embodiments, the light-emitting unit EMU (or the emissionareas EA corresponding to the light-emitting units EMU) may be locatedbetween a first line and a second line, each of which extending in thefirst direction DR1 and being spaced apart from each other in the seconddirection DR2. The first line and the second line may be immediatelyadjacent to the light-emitting units EMU in the second direction DR2.

For example, first, second, and third light-emitting units EMU1, EMU2,and EMU3 of the first pixel PXL1 (or first, second, and third emissionareas EA1, EA2, and EA3 corresponding to the first, second, and thirdlight-emitting units EMU1, EMU2, and EMU3 of the first pixel PXL1) maybe located between an nth scan line SLn for supplying a scan signal tothe first pixel PXL1 and a first horizontal power line HPL1, and may bearranged along the first direction DR1 between the nth scan line SLn andthe first horizontal power line HPL1. First, second, and thirdlight-emitting units EMU1, EMU2, and EMU3 of the second pixel PXL2 (orfirst, second, and third emission areas EA1, EA2, and EA3 correspondingto the first, second, and third light-emitting units EMU1, EMU2, andEMU3 of the second pixel PXL2) may be located between an (n+1)th scanline SLn+1 for supplying a scan signal to the second pixel PXL2 and asecond horizontal power line HPL2, and may be arranged along the firstdirection DR1 between the (n+1)th scan line SLn+1 and the secondhorizontal power line HPL2.

Each light-emitting unit EMU may include at least one pair of alignmentelectrodes ALE, at least one light-emitting element LD, and at least onepair of contact electrodes CNE. For example, each light-emitting unitEMU may include a first alignment electrode ALE1, a second alignmentelectrode ALE2, a third alignment electrode ALE3, first light-emittingelements LD1, second light-emitting elements LD2, a first contactelectrode CNE1, a second contact electrode CNE2, and a third contactelectrode CNE3, which are located in each emission area EA.

In each emission area EA, the first alignment electrode ALE1, the secondalignment electrode ALE2, and the third alignment electrode ALE3 may bespaced apart from each other along the first direction DR1, and each mayextend in the second direction DR2. The first light-emitting elementsLD1 may be located between the first alignment electrode ALE1 and thesecond alignment electrode ALE2, and the second light-emitting elementsLD2 may be located between the second alignment electrode ALE2 and thethird alignment electrode ALE3. That light-emitting elements LD arelocated between alignment electrodes ALE may mean that, when viewed on aplane, at least a portion of each of the light-emitting elements LD islocated in an area between the alignment electrodes ALE and/or at theperiphery thereof. The light-emitting elements LD may or may not overlapwith alignment electrodes ALE located at the periphery thereof.

In one or more embodiments, light-emitting elements LD may be preparedin a form in which the light-emitting elements LD are dispersed in asolution to be supplied to each emission area EA through an inkjetprinting process, or the like. For example, a light-emitting element inkincluding light-emitting elements LD may be supplied to each emissionarea EA defined by a first bank BNK1. When alignment signals arerespectively applied to alignment electrodes ALE (or alignment lines) ofsub-pixels SPX in a state in which light-emitting elements LD aresupplied to each emission area EA, the light-emitting elements LD may bealigned between the alignment electrodes ALE. For example, the firstlight-emitting elements LD1 may be aligned in a first light-emittingelement arrangement area AR1 such that first end portions EP1 of thefirst light-emitting elements LD1 are adjacent to the first alignmentelectrode ALE1, and such that second end portions EP2 of the firstlight-emitting elements LD1 are adjacent to the second alignmentelectrode ALE2. The second light-emitting elements LD2 may be aligned ina second light-emitting element arrangement area AR2 such that first endportions EP1 of the second light-emitting elements LD2 are adjacent tothe third alignment electrode ALE3, and such that second end portionsEP2 of the second light-emitting elements LD2 are adjacent to the secondalignment electrode ALE2. After the light-emitting elements LD arealigned, a solvent of the light-emitting element ink may be removedthrough a drying process or the like.

In one or more embodiments, first alignment electrodes ALE1, thirdalignment electrodes ALE3, and floating patterns FPT, which are providedin the display area DA, may be formed to be firstly connected to eachother in a pixel process, thereby constituting a first alignment line.Accordingly, in an alignment process of the light-emitting elements LD,a first alignment signal may be supplied to the first alignment linethrough the first power line PL1. After the alignment process of thelight-emitting elements LD is completed, the first alignment line may becut off at the periphery of third contact holes CH3, so that thefloating patterns FPT can be separated from the first alignmentelectrodes ALE1 (or the first alignment electrodes ALE1 and the thirdalignment electrodes ALE3).

In one or more embodiments, some alignment electrodes ALE oflight-emitting units EMU adjacent to each other in the first directionDR1 may be formed to be first connected to each other, therebyconstituting one alignment line, and may be separated from each other asindividual alignment electrodes ALE after the light-emitting element LDare completely aligned. For example, first alignment electrodes ALE1provided in a first light-emitting unit EMU1 of each pixel PXL may beformed to be connected to third alignment electrodes ALE3 provided in athird light-emitting unit EMU3 of another pixel PXL adjacent to thepixel PXL in the first direction DR1, thereby constituting one firstalignment line, and then may be separated from each other in asubsequent process. A first alignment electrode ALE1 provided in asecond light-emitting unit EMU2 of each pixel PXL may be formed to beconnected to a third alignment electrode ALE3 provided in a firstlight-emitting unit EMU1 of the corresponding pixel PXL, therebyconstituting one first alignment line, and then may be separated fromeach other in a subsequent process. A first alignment electrode ALE1provided in a third light-emitting unit EMU3 of each pixel PXL may beformed to be connected to a third alignment electrode ALE3 provided in asecond light-emitting unit EMU2 of the corresponding pixel PXL, therebyconstituting one first alignment line, and then may be separated fromeach other in a subsequent process.

In one or more embodiments, at least some of alignment electrodes ALEadjacent to each other in the second direction DR2 may be formed to befirst connected to each other, thereby constituting one alignment line,and may be separated from each other as individual alignment electrodesALE after the light-emitting element LD are completely aligned. Forexample, first alignment electrodes ALE1 may be continuously formedalong the second direction DR2 in the display area DA, therebyconstituting a first alignment line, and then may be separated from eachother as individual first alignment electrodes ALE1 by being cut offbetween emission areas EA adjacent to each other in the second directionDR2 after the light-emitting element LD are completely aligned. In oneor more embodiments, after the light-emitting element LD are completelyaligned, a first alignment line may be etched in a non-emission area NEAadjacent to each emission area EA in the second direction DR2.Therefore, the first alignment line may be separated into firstalignment electrodes ALE1 of sub-pixels SPX. Each first alignmentelectrode ALE may include an end portion located at a portion of anon-emission area NEA adjacent to an emission area EA of a correspondingsub-pixel SPX in the second direction DR2.

In one or more embodiments, third alignment electrodes ALE3 may becontinuously formed along the second direction DR2 in the display areaDA, and then may be separated from each other as individual thirdalignment electrodes ALE3 by being cut off between emission areas EAadjacent to each other in the second direction DR2 after thelight-emitting elements LD are completely aligned. Each third alignmentelectrode ALE3 may include an end portion located at a portion of anon-emission area NEA adjacent to an emission area EA of a correspondingsub-pixel SPX.

A first alignment electrode ALE1 of each sub-pixel SPX may beelectrically connected to a pixel circuit PXC of the correspondingsub-pixel SPX through each first contact hole CH1, and may beelectrically connected to a first contact electrode CNE1 of acorresponding light-emitting unit EMU through each fourth contact holeCH4. Also, the first alignment electrode ALE1 of each sub-pixel SPX maybe electrically connected to light-emitting elements LD of thecorresponding light-emitting unit EMU through the first contactelectrode CNE1. For example, each first alignment electrode ALE1 may beelectrically connected to first end portions EP1 of first light-emittingelements LD1 located in each emission area EA through each first contactelectrode CNE1.

In one or more embodiments, second alignment electrodes ALE2 of at leasttwo light-emitting units EMU adjacent to each other in the seconddirection DR2 may be connected to each other. For example, a secondalignment electrode ALE2 provided in the first light-emitting unit EMU1of the first pixel PXL1 and a second alignment electrode ALE2 providedin the first light-emitting unit EMU1 of the second pixel PXL2 may beintegrally formed, and may constitute one integrated second alignmentelectrode ALE2. In some embodiments, second alignment electrodes ALE2arranged in the second direction DR2 in the display area DA may beintegrally formed, but embodiments are not limited thereto. In analignment process of light-emitting elements LD, second alignmentelectrodes ALE2 may be connected to each other to constitute a secondalignment line. After the light-emitting elements LD are completelyaligned, second alignment electrodes ALE2 extending along the seconddirection DR2 in the display area DA may be separated from each other bybeing cut off in a unit of at least two pixel row, or may be integrallyformed without being cut off.

The second alignment electrodes ALE2 may be electrically connected to asecond power line PL2 (e.g., second horizontal power lines HPL2) throughsecond contact holes CH2. The second alignment electrodes ALE2 may besupplied with a second alignment signal through the second power linePL2 in an alignment process of the light-emitting elements LD. The firstalignment signal and the second alignment signal may have differentwaveforms, different phases, and/or different phases. Accordingly, anelectric field is formed between the first alignment line and the secondalignment electrodes ALE (or the second alignment line formed by thesecond alignment electrodes ALE2), so that the light-emitting elementsLD can be aligned between the first alignment line and the secondalignment electrodes ALE2. For example, first light-emitting elementsLD1 may be aligned in a first light-emitting element arrangement areaAR1 between a first alignment ALE1 and a second alignment electrode ALE2of light-emitting unit EMU, and second light-emitting elements LD2 maybe aligned in a second light-emitting element arrangement area AR2between the second alignment electrode ALE2 and a third alignmentelectrode ALE3 of the light-emitting unit EMU. Each light-emittingelement arrangement area AR may be surrounded by a bank pattern BNP.

When the display device DD is driven, the first power voltage VDD may beapplied to the first alignment electrodes ALE1 through the first powerline PL1 and the pixel circuit PXC, and the second power voltage VSS maybe applied to the second alignment electrodes ALE2 through the secondpower line PL2.

The first contact electrode CNE1 may be located on the first endportions EP1 of the first light-emitting elements LD1 and the firstalignment electrode ALE1. In one or more embodiments, the first contactelectrode CNE1 may be in contact with and/or electrically connected tothe first end portions EP1 of the first light-emitting elements LD1, andmay be electrically connected to the first alignment electrode ALE1through a fourth contact hole CH4. In one or more embodiments, thefourth contact hole CH4 may be formed in the first insulating layer INS1shown in FIG. 7 , and may be formed in a non-emission area NEA at theoutside of an emission area EA. In one or more embodiments, fourthcontact holes CH4 of sub-pixels SPX may be located at the outside of theemission area EA, and may be formed in an area not overlapping with thefirst bank BNK1. The fourth contact holes CH4 can be suitably formed ona relatively flat area while avoiding an area in which a step differencecaused by the first bank BNK1 occurs. The position of the fourth contacthole CH4 may be changed in some embodiments.

The second contact electrode CNE2 may be located on the second endportions EP2 of the first light-emitting elements LD, on a portion ofthe second alignment electrode ALE2, on the first end portions EP1 ofthe second light-emitting elements LD2, and on the third alignmentelectrode ALE3. In one or more embodiments, the second contact electrodeCNE2 may be an electrode having left/right pattern parts such as a “U”shape. The left pattern part of the second contact electrode CNE2 may belocated on the second end portions EP2 of the first light-emittingelements LD1 and on the portion of the second alignment electrode ALE2,and the right pattern part of the second contact electrode CNE2 may belocated on the first end portions EP1 of the second light-emittingelements LD2 and on the third alignment electrode ALE3. In one or moreembodiments, the second contact electrode CNE2 may be in contact withand/or electrically connected to the second end portions EP2 of thefirst light-emitting elements LD1 and to the first end portions EP1 ofthe second light-emitting elements LD2. The first light-emittingelements LD1 and the second light-emitting elements LD2 may be connectedin series to each other by the second contact electrode CNE2.

The third contact electrode CNE3 may be located on the second endportions EP2 of the second light-emitting elements LD2 and anotherportion of the second alignment electrode ALE2. In one or moreembodiments, the third contact electrode CNE3 may be in contact withand/or electrically connected to the second end portions EP2 of thesecond light-emitting elements LD2, and may be electrically connected tothe second alignment electrode ALE2 through a fifth contact hole CH5. Inone or more embodiments, the fifth contact hole CH5 may be formed in thefirst insulating layer INS1 shown in FIG. 7 , and may be formed in thenon-emission area NEA at the outside of the emission area EA. In one ormore embodiments, fifth contact holes CH5 of sub-pixels SPX may belocated at the outside of the emission area EA, and may be formed in anarea not overlapping with the first bank BNK1. The fifth contact holesCH5 can be suitably formed on a relatively flat area while avoiding anarea in which a step different caused by the first bank BNK1 occurs. Thepositions of the fifth contact holes CH5 may be changed in someembodiments.

The shapes, sizes, numbers, positions, and/or mutual arrangementstructure of alignment electrodes ALE and contact electrodes CNE may bechanged in some embodiments.

Bank patterns BNP may be located on the bottom of the alignmentelectrodes ALE. In one or more embodiments, the bank patterns BNP may beformed as individual patterns formed to be separated from each other,corresponding to each pixel PXL as shown in FIG. 10 . For example,pixels PXL (e.g., a first pixel PXL1 and a third pixel PXL3, or a secondpixel PXL2 and a fourth pixel PXL4) that each include sub-pixels SPX,and that are arranged in the first direction DR1, may include bankpatterns BNP separated from each other. In one or more otherembodiments, as shown in FIG. 11 , bank patterns BNP corresponding to atleast two pixels PXL adjacent to each other in the first direction DR1(e.g., provided to the at least two pixels PXL) may be integrally formedto substantially form one bank pattern BNP. In one or more embodiments,one integrated bank pattern BNP may be located for every horizontal lineof the display area DA.

Each bank pattern BNP may include/define openings OPN respectivelycorresponding to light-emitting element arrangement areas AR providedemission area EA of a corresponding pixel PXL. For example, each bankpattern BNP may include first openings OPN1 corresponding to firstlight-emitting element arrangement areas AR1 provided in first, second,and third light-emitting units EMU1, EMU2, and EMU3 of a correspondingpixel PXL, and second openings OPN2 corresponding to secondlight-emitting element arrangement areas AR2 provided to the first,second, and third light-emitting units EMU1, EMU2, and EMU3 of thecorresponding pixel PXL. In one or more embodiments, the bank patternsBNP may further include third openings OPN3 formed between emissionareas EA of the corresponding pixel PXL.

In one or more embodiments, emission areas EA of each pixel PXL (e.g., afirst emission area EA1 of a first light-emitting unit EMU1, a secondemission area EA2 of a second light-emitting unit EMU2, and a thirdemission area EA3 of a third light-emitting unit EMU3) may be located inan area between two lines (hereinafter, referred to as a “first line”and a “second line”) that each extend in the first direction, and thatare spaced apart from each other in the second direction DR2. In one ormore embodiments, the first, second, and third emission areas EA1, EA2,and EA3 of each pixel PXL may be arranged in the first direction DR1 inthe area between the first line and the second line.

For example, first, second, and third emission areas EA1, EA2, and EA3of the first pixel PXL1 may be located between an nth scan line SLn anda first horizontal power line HPL1 in the second direction DR2, and maybe arranged in the first direction DR1 between the nth scan line SLn andthe first horizontal power line HPL1. First, second, and third emissionareas EA1, EA2, and EA3 of the second pixel PXL2 may be located betweenan (n+1)th scan line SLn+1 and a second horizontal power line HPL2 inthe second direction DR2, and may be arranged in the first direction DR1therebetween.

A bank pattern BNP of each pixel PXL may overlap with the first line andthe second line. For example, a bank pattern BNP corresponding to thefirst pixel PXL1 (e.g., a bank pattern BNP formed in the first pixelPXL1) may overlap with the nth scan line SLn and the first horizontalpower line HPL1, and a bank pattern BNP corresponding to the secondpixel PXL2 (e.g., a bank pattern BNP formed in the second pixel PXL2)may overlap with the (n+1)th scan line SLn+1 and the second horizontalpower line HPL2.

In one or more embodiments, bank patterns BNP of sub-pixels SPX providedin each pixel PXL may be connected to each other in the first directionDR1. Therefore, the bank patterns BNP may be substantially formed as onebank pattern BNP. Each bank pattern BNP may include a first pattern partBNP_1 and a second pattern part BNP_2 respectively adjacent to firstedge areas and second edge areas of emission areas EA provided in acorresponding pixel PXL. The first edge areas and the second edge areasof the emission areas EA may be located at both ends of the emissionareas EA in the second direction DR2. The first pattern part BNP_1 andthe second pattern part BNP_2 of the bank pattern BNP may overlap with afirst line and a second line of a corresponding pixel PXL and/or acorresponding horizontal line. For example, the first pattern part BNP_1of the bank pattern BNP may overlap with a first line (e.g., a scan lineSLn electrically connected to the corresponding pixel PXL) adjacent tothe first edge areas of the emission areas EA provided in thecorresponding pixel PXL, and the second pattern part BNP_2 of the bankpattern BNP may overlap with a second line (e.g., a first horizontalpower line HPL1 or a second horizontal power line HPL2, which is locatedbetween second and third pixel circuits PXC2 and PXC3 of thecorresponding horizontal line) adjacent to the second edge areas of theemission areas EA provided in the corresponding pixel PXL. In addition,each bank pattern BNP may further include a third pattern part BNP_3that extends in a direction that is different from a direction in whichthe first pattern part BNP_1 and the second pattern part BNP_2 extend,and that connects the first pattern part BNP_1 and the second patternpart BNP_2 to each other.

For example, the bank pattern BNP of the first pixel PXL1 may include afirst pattern part BNP_1 that overlaps with an nth scan line SLn, andthat is continuously formed along the first direction DR1 at theperiphery of the emission areas EA of the first pixel PXL1 (e.g., aportion immediately adjacent to the first edge areas of the first,second, and third emission areas EA1, EA2, and EA3 of the first pixelPXL1), and a second pattern part BNP_2 that overlaps with a firsthorizontal power line HPL1 (e.g., a first horizontal power line HPL1located between second and third pixel circuits PXC2 and PXC3 of thefirst pixel PXL1), and that is continuously formed along the firstdirection DR1 at the periphery of the emission areas EA of the firstpixel PXL1 (e.g., a portion immediately adjacent to the second edgeareas of the first, second, and third emission areas EA1, EA2, and EA3of the first pixel PXL1). In addition, the bank pattern BNP of the firstpixel PXL1 may include third pattern parts BNP_3 located at both sidesof each light-emitting element arrangement area AR of the first pixelPXL1 in the first direction DR1. The third pattern parts BNP_3 mayextend in the second direction DR2.

Similarly, the bank pattern BNP of the second pixel PXL2 may include afirst pattern part BNP_1 that overlaps with an (n+1)th scan line SLn,and that is continuously formed along the second direction DR1 at theperiphery of the emission areas EA of the first pixel PXL2 (e.g., aportion immediately adjacent to the first edge areas of the first,second, and third emission areas EA1, EA2, and EA3 of the second pixelPXL2), and a second pattern part BNP_2 that overlaps with a secondhorizontal power line HPL2 (e.g., a second horizontal power line HPL2located between second and third pixel circuits PXC2 and PXC3 of thesecond pixel PXL2), and that is continuously formed along the firstdirection DR1 at the periphery of the emission areas EA of the secondpixel PXL2 (e.g., a portion immediately adjacent to the second edgeareas of the first, second, and third emission areas EA1, EA2, and EA3of the second pixel PXL2). In addition, the bank pattern BNP of thesecond pixel PXL2 may include third pattern parts BNP_3 located at bothsides of each light-emitting element arrangement area AR of the secondpixel PXL2 in the first direction DR1. The third pattern parts BNP_3 mayextend in the second direction DR2.

A first bank BNK1 may be located in the display area DA in which bankpatterns BNP, alignment electrodes ALE, and the like are located. Thefirst bank BNK1 may include openings OPN corresponding emission areas EAof sub-pixels SPX, and surround the emission areas EA.

The first bank BNK1 may be located in a portion of the non-emission areaNEA. For example, the first bank BNK1 may be opened between two adjacentpixel rows. In one or more embodiments, the first bank BNK1 may beopened at least a portion of areas in which a first alignment line iscut off to separate the first alignment line into individual firstalignment electrodes ALE1 (e.g., a peripheral area of floating patternsFPT and an area between adjacent pixel rows).

The first bank BNK1 may overlap with a first line, a second line, and abank pattern BNP in an area in which the first line and the second line,which are adjacent to emission areas EA of a corresponding horizontalline (e.g., each pixel row) in the second direction DR2. In one or moreembodiments, the first bank BNK1 may be continuously formed along thefirst direction DR1 at a portion at which the first bank BNK1 overlapswith the first line, the second line, and the bank pattern BNP. Forexample, the first line (e.g., a scan line SL of a correspondinghorizontal line), the bank pattern BNP (e.g., the first pattern partBNP_1 of the bank pattern BNP), and the first bank BNK1 may completelyoverlap with each other in a non-emission area NEA immediately adjacentto first edge areas of first, second, and third emission areas EA1, EA2,and EA3 of each pixel PXL. Similarly, the second line (e.g., a firsthorizontal power line HPL1 or a second horizontal power line HPL2, whichis located on the corresponding horizontal line), the bank pattern BNK(e.g., the second pattern part BNP_2 of the bank pattern BNP), and thefirst bank BNK1 may completely overlap with each other in a non-emissionarea NEA immediately adjacent to second edge areas of first, second, andthird emission areas EA1, EA2, and EA3 of each pixel PXL. In one or moreembodiments, the first line and the second line may be provided in aconductive layer (e.g., a third conductive layer) located relativelyclose the display layer DPL (e.g., closest to the display layer DPL)among conductive layers provided in the circuit layer PCL.

As described above, in a non-emission area NEA adjacent to both ends ofemission areas EA in at least the second direction DR2, the first orsecond line, the bank pattern BNP, and the first bank BNK1 overlap witheach other, so that the height of the first bank BNK1 can be increasedor maximized. For example, in a non-emission area NEA immediatelyadjacent to second edge areas (bottom edge areas) of emission areas EA,the first horizontal power line HPL1, the bank pattern BNP, and thefirst bank BNK1 may continuously overlap with each other along the firstdirection DR1 as shown in FIG. 12 .

At the portion at which the first bank BNK1 overlaps with the firsthorizontal power line HPL1 and the bank pattern BNP, the first bank BNK1may be formed relatively high, as compared with a portion at which thefirst bank BNK1 does not overlap with the first horizontal power lineHPL1 and/or the bank pattern BNP. Accordingly, in a process of supplyinga light-emitting element ink including light-emitting elements LD ineach emission area EA defined by the first bank BNK1, the capacity ofthe light-emitting element ink that can be accommodated in each emissionarea EA can be increased, and overflow of the light-emitting element inkover the non-emission area NEA can be prevented or reduced.

As described above, the display device DD in accordance with theembodiments of the present disclosure may include a first line (e.g., ascan line SL of each horizontal line) extending in the first directionDR1, a second line (e.g., a first horizontal power line HPL1 or a secondhorizontal power line HPL2) spaced apart from the first line in thesecond direction DR2, emission areas EA (e.g., first, second, and thirdemission areas EA1, EA2, and EA3) located between the first line and thesecond line, sub-pixels SPX (e.g., first, second, and third sub-pixelsSPX1, SPX2, and SPX3) including light-emitting elements LD located inthe emission areas EA, a bank pattern BNP that overlaps with the firstline and the second line and that includes openings respectivelycorresponding to light-emitting element arrangement areas AR in whichthe light-emitting elements LD are arranged, and a first bank BNK1 thatsurrounds the emission areas EA and overlaps with the first line, thesecond line, and the bank pattern BNP. In accordance with theembodiments of the present disclosure, in a non-emission area NAimmediately adjacent to both ends of emission areas EA of sub-pixels SPXin the second direction DR2, the height of the first bank BNK1 can beincreased or maximized. Accordingly, the capacity amount of emissionareas EA can be increased, and overflow of a light-emitting element inkover the non-emission area NEA at the periphery of the emission area EA(e.g., the non-emission area NEA adjacent to both ends of the emissionareas EA in the second direction DR2) in a process of supplying thelight-emitting elements LD to the emission areas EA can be prevented orreduced. Accordingly, a first alignment line can be stably separatedinto individual first alignment electrodes ALE1 in a subsequent process.In addition, the likelihood of a short-circuit defect that may occurbecause first alignment electrodes ALE1 are not separated can beprevented and reduced.

In the display device in accordance with the present disclosure, in anon-emission area adjacent to emission area of sub-pixels, a first orsecond line, a bank pattern, and a first bank overlap with each other,so that the height of the first bank can be increased or maximized.Accordingly, the capacity amount of emission areas can be increased, andoverflow of a light-emitting element ink including light-emittingelements over the non-emission area in a process of supplying thelight-emitting elements to the emission areas can be prevented orreduced. Thus, a first alignment line can be stably separated into firstalignment electrodes in a sub-sequent process, and the likelihood of ashort-circuit defect can be prevented or reduced.

Embodiments have been disclosed herein, and although specific terms areemployed, they are used and are to be interpreted in a generic anddescriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with one or more embodiments maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments, unlessotherwise specifically indicated. Accordingly, it will be understood bythose of skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentdisclosure as set forth in the following claims, with functionalequivalents thereof to be included therein.

What is claimed is:
 1. A display device comprising: a first lineextending in a first direction; a second line spaced apart from thefirst line in a second direction; sub-pixels comprising emission areasbetween the first line and the second line; light-emitting elements inlight-emitting element arrangement areas in the emission areas; a bankpattern overlapping with the first line and the second line, anddefining openings corresponding to the light-emitting elementarrangement areas; and a bank surrounding the emission areas, andoverlapping with the first line, the second line, and the bank pattern.2. The display device of claim 1, wherein the second line extends in thefirst direction, and wherein the bank pattern comprises: a first patternpart overlapping the first line, and continuously formed along the firstdirection at a periphery of the emission areas; a second pattern partoverlapping the second line, and continuously formed along the firstdirection at the periphery of the emission areas; and third patternparts at respective sides of the light-emitting element arrangementareas in the first direction, and extending in the second direction. 3.The display device of claim 2, wherein the bank is continuously formedalong the first direction at a portion overlapping with the firstpattern part and the second pattern part.
 4. The display device of claim1, wherein the first line is a scan line configured to transmit a scansignal, and wherein the second line is a power line configured totransmit a first power voltage or a second power voltage.
 5. The displaydevice of claim 1, wherein the sub-pixels comprise a first alignmentelectrode at a periphery of first end portions of the light-emittingelements, and extending in the second direction, and wherein the firstalignment electrode comprises an end portion at a portion of anon-emission area adjacent to an emission area of a correspondingsub-pixel in the second direction.
 6. The display device of claim 5,wherein the first alignment electrode is electrically connected to thefirst end portions of the light-emitting elements.
 7. The display deviceof claim 6, wherein the sub-pixels further comprise a pixel circuitelectrically connected to the first alignment electrode.
 8. The displaydevice of claim 5, wherein the sub-pixels further comprise a secondalignment electrode at a periphery of second end portions of thelight-emitting elements, and extending in the second direction.
 9. Thedisplay device of claim 8, further comprising a power line electricallyconnected to the second alignment electrode.
 10. The display device ofclaim 1, wherein the sub-pixels comprise a first sub-pixel, a secondsub-pixel, and a third sub-pixel, which constitute one pixel, andrespectively comprise a first emission area, a second emission area, anda third emission area, and that are arranged in the first directionbetween the first line and the second line.
 11. The display device ofclaim 10, wherein the first line, the bank pattern, and the bankcompletely overlap with each other in a non-emission area immediatelyadjacent to first edge areas of the first emission area, the secondemission area, and the third emission area, and wherein the second line,the bank pattern, and the bank completely overlap with each other in anon-emission area immediately adjacent to second edge areas of the firstemission area, the second emission area, and the third emission area.12. The display device of claim 10, wherein the first sub-pixel furthercomprises a first pixel circuit electrically connected to light-emittingelements in the first emission area among the light-emitting elements,wherein the second sub-pixel further comprises a second pixel circuitelectrically connected to light-emitting elements in the second emissionarea among the light-emitting elements, and wherein the third sub-pixelfurther comprises a third pixel circuit electrically connected tolight-emitting elements in the third emission area among thelight-emitting elements.
 13. The display device of claim 12, wherein thefirst pixel circuit, the second pixel circuit, and the third pixelcircuit are arranged in the second direction.
 14. The display device ofclaim 13, wherein the second line is between the second pixel circuitand the third pixel circuit.
 15. The display device of claim 13, whereinthe first pixel circuit and the third pixel circuit are between thefirst line and the second line.
 16. The display device of claim 1,wherein the sub-pixels comprise: a light-emitting unit comprising atleast one light-emitting element in a corresponding emission area amongthe light-emitting elements, and electrodes electrically connected tothe at least one light-emitting element; and a pixel circuit comprisingcircuit elements electrically connected to the light-emitting unit. 17.The display device of claim 16, further comprising: a circuit layercomprising pixel circuits of the sub-pixels, the first line, and thesecond line; and a display layer overlapping with the circuit layer, andcomprising light-emitting units of the sub-pixels.
 18. The displaydevice of claim 17, wherein the circuit layer comprises conductivelayers sequentially arranged along a third direction crossing the firstdirection and the second direction, and wherein a conductive layerclosest to the display layer among the conductive layers comprises thefirst line and the second line.
 19. The display device of claim 1,further comprising at least two pixels each comprising sub-pixels amongthe sub-pixels, the at least two pixels being arranged in the firstdirection, wherein the bank pattern comprises individual patterns formedby separating patterns corresponding to the at least two pixels fromeach other, or comprises an integrated pattern in which patternscorresponding to the at least two pixels are integrally formed.
 20. Adisplay device comprising: a first line and a second line extending in afirst direction, and spaced apart from each other in a second direction;a first sub-pixel comprising first light-emitting elements in a firstemission area between the first line and the second line; a secondsub-pixel comprising second light-emitting elements in a second emissionarea that is adjacent to the first emission area in the first direction,and that is between the first line and the second line; a thirdsub-pixel comprising third light-emitting elements in a third emissionarea that is adjacent to the second emission area in the firstdirection, and that is between the first line and the second line; abank pattern overlapping with the first line and the second line, anddefining openings respectively corresponding to light-emitting elementarrangement areas in the first emission area, the second emission area,and the third emission area; and a bank surrounding the first to thirdemission areas, and overlapping with the first line, the second line,and the bank pattern, wherein, at a portion immediately adjacent to bothends of the first emission area, the second emission area, and the thirdemission area in the second direction, the bank pattern and the bankoverlap with the first line and the second line and are continuouslyformed along the first direction.